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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/6] drm/i915: Always load the display palette before enabling the pipe
Date: Wed, 8 May 2013 14:29:20 -0700	[thread overview]
Message-ID: <20130508142920.0ee6c78d@jbarnes-desktop> (raw)
In-Reply-To: <1368006628-24628-2-git-send-email-ville.syrjala@linux.intel.com>

On Wed,  8 May 2013 12:50:23 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Loading the palette after the planes are enabled can risk showing
> incorrect colors. ILK+ already load the palette before even the pipe
> is enabled. Just follow the same order for gen2-4 and VLV.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b0e29e2..40e014af 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3683,10 +3683,11 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  	/* Enable panel fitting for eDP */
>  	i9xx_pfit_enable(intel_crtc);
>  
> +	intel_crtc_load_lut(crtc);
> +
>  	intel_enable_pipe(dev_priv, pipe, false);
>  	intel_enable_plane(dev_priv, plane, pipe);
>  
> -	intel_crtc_load_lut(crtc);
>  	intel_update_fbc(dev);
>  
>  	/* Give the overlay scaler a chance to enable if it's on this pipe */
> @@ -3722,12 +3723,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	/* Enable panel fitting for LVDS */
>  	i9xx_pfit_enable(intel_crtc);
>  
> +	intel_crtc_load_lut(crtc);
> +
>  	intel_enable_pipe(dev_priv, pipe, false);
>  	intel_enable_plane(dev_priv, plane, pipe);
>  	if (IS_G4X(dev))
>  		g4x_fixup_plane(dev_priv, pipe);
>  
> -	intel_crtc_load_lut(crtc);
>  	intel_update_fbc(dev);
>  
>  	/* Give the overlay scaler a chance to enable if it's on this pipe */

So it's just the pll that we need to have running in this case, not the
pipe?  I guess we'd find out quickly enough, the failure mode is a hard
system hang...
-- 
Jesse Barnes, Intel Open Source Technology Center
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  reply	other threads:[~2013-05-08 21:28 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-05-08  9:50 [PATCH 0/6] drm/i915: Unfify some modeset sequences ville.syrjala
2013-05-08  9:50 ` [PATCH 1/6] drm/i915: Always load the display palette before enabling the pipe ville.syrjala
2013-05-08 21:29   ` Jesse Barnes [this message]
2013-05-31 17:09     ` [PATCH v2] " ville.syrjala
2013-05-31 18:59       ` Daniel Vetter
2013-05-08  9:50 ` [PATCH 2/6] drm/i915: Always enable the cursor right after the primary plane ville.syrjala
2013-05-21 15:17   ` Egbert Eich
2013-05-22 11:15     ` Ville Syrjälä
2013-05-23 11:07       ` Egbert Eich
2013-06-06 16:30     ` Egbert Eich
2013-06-06 17:34       ` Ville Syrjälä
2013-05-08  9:50 ` [PATCH 3/6] drm/i915: Enable the overlay right after primary and cursor planes ville.syrjala
2013-05-08  9:50 ` [PATCH 4/6] drm/i915: Follow the same sequence when disabling planes ville.syrjala
2013-05-08  9:50 ` [PATCH 5/6] drm/i915: Drop overlay DPMS call from valleyview_crtc_enable ville.syrjala
2013-05-08  9:50 ` [PATCH 6/6] drm/i915: Disable/restore all sprite planes around modeset ville.syrjala

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