Re: [PATCH v2 1/3] drm/i915: Disable primary plane trickle feed for g4x

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The docs say that the trickle feed disable bit is present (for primary
> planes only, not video sprites) on CTG, and that it must be set
> for ELK. Just set it for all g4x chipsets.
> 
> v2: Do it in init_clock_gating too

Actually I just noticed that we don't set up this stuff in
ironlake_init_clock_gating() either. Any opinions whether I should just
kill the per-plane trickle feed stuff from *_init_clock_gating(), or
should I add it to ironlake_init_clock_gating() as well?

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c      | 9 +++++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 684ab64..c8b033a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2041,6 +2041,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>  			dspcntr &= ~DISPPLANE_TILED;
>  	}
>  
> +	if (IS_G4X(dev))
> +		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> +
>  	I915_WRITE(reg, dspcntr);
>  
>  	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8a90cf3..cf0f658 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4390,6 +4390,7 @@ static void g4x_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t dspclk_gate;
> +	int pipe;
>  
>  	I915_WRITE(RENCLK_GATE_D1, 0);
>  	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> @@ -4406,6 +4407,14 @@ static void g4x_init_clock_gating(struct drm_device *dev)
>  	/* WaDisableRenderCachePipelinedFlush */
>  	I915_WRITE(CACHE_MODE_0,
>  		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
> +
> +	for_each_pipe(pipe) {
> +		I915_WRITE(DSPCNTR(pipe),
> +			   I915_READ(DSPCNTR(pipe)) |
> +			   DISPPLANE_TRICKLE_FEED_DISABLE);
> +		intel_flush_display_plane(dev_priv, pipe);
> +	}
> +
>  }
>  
>  static void crestline_init_clock_gating(struct drm_device *dev)
> -- 
> 1.8.1.5

-- 
Ville Syrjälä
Intel OTC