Re: [Intel-gfx] [PATCH 1/6] drm/i915: Serialize almost all register access

[Daniel Vetter <daniel@ffwll.ch>]

On Fri, Jul 19, 2013 at 08:36:51PM +0100, Chris Wilson wrote:
> In theory, the different register blocks were meant to be only ever
> touched when holding either the struct_mutex, mode_config.lock or even a
> specific localised lock. This does not seem to be the case, and the
> hardware reacts extremely badly if we attempt to concurrently access two
> registers within the same cacheline.
> 
> The HSD suggests that we only need to do this workaround for display
> range registers. However, upon review we need to serialize the multiple
> stages in our register write functions - if only for preemption
> protection.
> 
> Irrespective of the hardware requirements, the current io functions are
> a little too loose with respect to the combination of pre- and
> post-condition testing that we do in conjunction with the actual io. As
> a result, we may be pre-empted and generate both false-postive and
> false-negative errors.
> 
> Note well that this is a "90%" solution, there remains a few direct
> users of ioread/iowrite which will be fixed up in the next few patches.
> Since they are more invasive and that this simple change will prevent
> almost all lockups on Haswell, we kept this patch simple to facilitate
> backporting to stable.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63914
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@vger.kernel.org
Picked up for -fixes, thanks for the patch. For the others I need to
backmerge first before I can slurp them in.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch