From: Daniel Vetter <daniel@ffwll.ch>
To: "Yang, Guang A" <guang.a.yang@intel.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Updated drm-intel-testing tree
Date: Fri, 26 Jul 2013 21:52:56 +0200 [thread overview]
Message-ID: <20130726195256.GO6084@phenom.ffwll.local> (raw)
Hi all,
New feature tree pushed, hightlights:
- proper eLLC support for HSW from Ben
- more interrupt refactoring
- add w/a tags where we implement them already (Damien)
- hangcheck fixes (Chris) + hangcheck stats (Mika)
- flesh out the new vm structs for ppgtt and ggtt (Ben)
- PSR for Haswell, still disabled by default (Rodrigo et al.)
- pc8+ refclock sequence code from Paulo
- more interrupt refactoring from Paulo, unifying ilk/snb with the ivb/hsw
interrupt code
- full solution for the Haswell concurrent reg access issues (Chris)
- fix racy object accounting, used by some new leak tests
- fix sync polarity settings on ch7xxx dvo encoder
- random bits&pieces, little fixes and better debug output all over
Happy testing!
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next reply other threads:[~2013-07-26 19:52 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-26 19:52 Daniel Vetter [this message]
-- strict thread matches above, loose matches on Subject: below --
2013-07-12 19:48 Updated drm-intel-testing tree Daniel Vetter
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