From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Capture batchbuffer state upon GPU hang
Date: Wed, 30 Oct 2013 10:14:28 +0100 [thread overview]
Message-ID: <20131030091427.GC4167@phenom.ffwll.local> (raw)
In-Reply-To: <1383077344-19985-1-git-send-email-chris@chris-wilson.co.uk>
On Tue, Oct 29, 2013 at 08:09:04PM +0000, Chris Wilson wrote:
> The bbstate contains useful bits of debugging information such as
> whether the batch is being read from GTT or PPGTT, or whether it is
> allowed to execute privileged instructions.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 3 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3d65b511e320..ca1b223356eb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -301,6 +301,7 @@ struct drm_i915_error_state {
> u32 cpu_ring_tail[I915_NUM_RINGS];
> u32 error; /* gen6+ */
> u32 err_int; /* gen7 */
> + u32 bbstate[I915_NUM_RINGS];
> u32 instpm[I915_NUM_RINGS];
> u32 instps[I915_NUM_RINGS];
> u32 extra_instdone[I915_NUM_INSTDONE_REG];
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 918d978dce4a..cdd9121a28bb 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -251,6 +251,7 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
> if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
> err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
>
> + err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]);
This seems to only exist on gen4+
-Daniel
> if (INTEL_INFO(dev)->gen >= 4)
> err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
> err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
> @@ -735,6 +736,7 @@ static void i915_record_ring_state(struct drm_device *dev,
> }
>
> error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
> + error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
> error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
> error->seqno[ring->id] = ring->get_seqno(ring, false);
> error->acthd[ring->id] = intel_ring_get_active_head(ring);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dbad19f4a983..9d79d28decb6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -722,6 +722,7 @@
> #define NOPID 0x02094
> #define HWSTAM 0x02098
> #define DMA_FADD_I8XX 0x020d0
> +#define RING_BBSTATE(base) ((base)+0x110)
>
> #define ERROR_GEN6 0x040a0
> #define GEN7_ERR_INT 0x44040
> --
> 1.8.4.rc3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2013-10-30 9:14 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-29 20:09 [PATCH] drm/i915: Capture batchbuffer state upon GPU hang Chris Wilson
2013-10-30 9:14 ` Daniel Vetter [this message]
-- strict thread matches above, loose matches on Subject: below --
2013-10-30 9:28 Chris Wilson
2013-10-30 9:38 ` Daniel Vetter
2013-10-30 9:46 ` Daniel Vetter
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