public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: Report all GTFIFODBG errors
Date: Thu, 14 Nov 2013 19:09:48 +0200	[thread overview]
Message-ID: <20131114170947.GO7819@intel.com> (raw)
In-Reply-To: <87d2m3gn4d.fsf@gaia.fi.intel.com>

On Thu, Nov 14, 2013 at 02:54:10PM +0200, Mika Kuoppala wrote:
> ville.syrjala@linux.intel.com writes:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > On VLV GTFIFODBG has more bits. Just report them all.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h     | 5 ++++-
> >  drivers/gpu/drm/i915/intel_uncore.c | 5 ++---
> >  2 files changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 849e595..e8f47de 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4852,7 +4852,10 @@
> >  #define    FORCEWAKE_MT_ENABLE			(1<<5)
> >  
> >  #define  GTFIFODBG				0x120000
> > -#define    GT_FIFO_CPU_ERROR_MASK		7
> > +#define    GT_FIFO_SBDROPERR			(1<<6)
> > +#define    GT_FIFO_BLOBDROPERR			(1<<5)
> > +#define    GT_FIFO_SB_READ_ABORTERR		(1<<4)
> > +#define    GT_FIFO_DROPERR			(1<<3)
> >  #define    GT_FIFO_OVFERR			(1<<2)
> >  #define    GT_FIFO_IAWRERR			(1<<1)
> >  #define    GT_FIFO_IARDERR			(1<<0)
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 0edabbb..a9849ab 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> >  	u32 gtfifodbg;
> >  
> >  	gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
> > -	if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
> > -	     "MMIO read or write has been dropped %x\n", gtfifodbg))
> > -		__raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
> > +	if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
> 
> I think you still need mask, there are ro fields != 0 in the same
> register.

Which bits? VLV has those seven low bits, others just three low bits
AFAICS.

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2013-11-14 17:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-13 23:59 [PATCH 0/2] drm/i915: VLV GT wake FIFO stuff ville.syrjala
2013-11-13 23:59 ` [PATCH 1/2] drm/i915: Report all GTFIFODBG errors ville.syrjala
2013-11-14 12:54   ` Mika Kuoppala
2013-11-14 17:09     ` Ville Syrjälä [this message]
2013-11-18 15:13       ` Ville Syrjälä
2013-11-20 17:14         ` Ville Syrjälä
2013-11-27 16:53           ` Jesse Barnes
2013-11-14  0:00 ` [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV ville.syrjala
2013-11-27 17:04   ` Jesse Barnes
2013-11-27 17:16     ` Daniel Vetter

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20131114170947.GO7819@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=mika.kuoppala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox