From: Daniel Vetter <daniel@ffwll.ch>
To: kirankumar <kiran.s.kumar@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] VPG [BDW] drm/i915/bdw: DP aux channel control timeout change
Date: Tue, 26 Nov 2013 10:24:39 +0100 [thread overview]
Message-ID: <20131126092439.GI27344@phenom.ffwll.local> (raw)
In-Reply-To: <1385453517-11477-1-git-send-email-kiran.s.kumar@intel.com>
On Tue, Nov 26, 2013 at 01:41:57PM +0530, kirankumar wrote:
> changing DP AUX control timeout to 600 instead of 400 for BDW.
DP spec says 400 us, so a notch more context in the commit message would
be appreciated. E.g. if this is used to work around dp aux failures, then
the commit message _must_ mention this. I need this to asses in which
branch to put the patch.
Also we still have occasional dp aux woes on older platforms. Do we need a
similar timeout extension for those, too?
Remember people: The commit message must explain _why_ something needs to
change. If you feel like you need to explain the what of your change, your
code probably needs to be rewritten to be esier to understand.
Cheers, Daniel
>
> Change-Id: Id507ef35490e12bbd896492c9da24d0db367bf1a
> Signed-off-by: kirankumar <kiran.s.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ae2a057..953a3f6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -351,7 +351,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> I915_WRITE(ch_ctl,
> DP_AUX_CH_CTL_SEND_BUSY |
> (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
> - DP_AUX_CH_CTL_TIME_OUT_400us |
> + DP_AUX_CH_CTL_TIME_OUT_600us |
> (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
> (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2013-11-26 9:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-26 8:11 [PATCH] VPG [BDW] drm/i915/bdw: DP aux channel control timeout change kirankumar
2013-11-26 9:24 ` Daniel Vetter [this message]
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