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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Fix the interlace mode selection for gmch platforms
Date: Fri, 28 Mar 2014 15:10:09 -0700	[thread overview]
Message-ID: <20140328151009.37423e09@jbarnes-desktop> (raw)
In-Reply-To: <1396042172-32495-3-git-send-email-ville.syrjala@linux.intel.com>

On Fri, 28 Mar 2014 23:29:31 +0200
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> PIPECONF_INTERLACE_W_FIELD_INDICATION is only meant to be used for sdvo
> since it implies a slightly weird vsync shift of htotal/2. For everything
> else we should use PIPECONF_INTERLACE_W_SYNC_SHIFT and let the value in
> the VSYNCSHIFT register take effect.
> 
> The only exception is gen3 simply because VSYNCSHIFT didn't exist yet.
> Gen2 doesn't support interlaced modes at all, so we can drop the
> explicit gen2 checks.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a9a4f6a..3ab40e3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5543,13 +5543,13 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  		}
>  	}
>  
> -	if (IS_VALLEYVIEW(dev) &&
> -	    intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> -		pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
> -	else if (!IS_GEN2(dev) &&
> -		 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> -		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> -	else
> +	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> +		if (INTEL_INFO(dev)->gen < 4 ||
> +		    intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
> +			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> +		else
> +			pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
> +	} else
>  		pipeconf |= PIPECONF_PROGRESSIVE;
>  
>  	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)

Hooray for SDVO.  I really hope no one tries to do that on VLV...
(afaik it's unsupported but who knows the hw might work if someone
solders such a board together).

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2014-03-28 22:09 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-28 21:29 [PATCH 0/3] drm/i915: Some vsyncshift fixes ville.syrjala
2014-03-28 21:29 ` [PATCH 1/3] drm/i915: Program VSYNCSHIFT in a more consistent manner ville.syrjala
2014-03-28 22:08   ` Jesse Barnes
2014-03-28 21:29 ` [PATCH 2/3] drm/i915: Fix the interlace mode selection for gmch platforms ville.syrjala
2014-03-28 22:10   ` Jesse Barnes [this message]
2014-03-28 21:29 ` [PATCH 3/3] drm/i915: Make sure vsyncshift is positive ville.syrjala
2014-03-28 22:11   ` Jesse Barnes
2014-03-29  9:40     ` Daniel Vetter

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