Re: [PATCH 3/6] drm/i915: Implement GPU reset for 915/945

From: Daniel Vetter <daniel@ffwll.ch>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/6] drm/i915: Implement GPU reset for 915/945
Date: Tue, 25 Nov 2014 13:54:43 +0100	[thread overview]
Message-ID: <20141125125443.GF25711@phenom.ffwll.local> (raw)
In-Reply-To: <1416599670-21914-4-git-send-email-ville.syrjala@linux.intel.com>

On Fri, Nov 21, 2014 at 09:54:27PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> 915/945 have the same reset registers as 965, so share the code.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I didn't find the gmch docs anywhere for these. Care to share?

Anyway, merged the first 6 patches from this series to dinq, thanks.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c     |  3 ++-
>  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
>  drivers/gpu/drm/i915/intel_uncore.c | 24 ++++++++++++------------
>  3 files changed, 15 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 68e4239..44abd7b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -881,7 +881,8 @@ int i915_reset(struct drm_device *dev)
>  		if (INTEL_INFO(dev)->gen > 5)
>  			intel_reset_gt_powersave(dev);
>  
> -		if (IS_GEN4(dev) && !IS_G4X(dev)) {
> +		if ((IS_GEN3(dev) && !IS_G33(dev)) ||
> +		    (IS_GEN4(dev) && !IS_G4X(dev))) {
>  			intel_runtime_pm_disable_interrupts(dev_priv);
>  			intel_runtime_pm_enable_interrupts(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ff1e36f..5446758 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -78,7 +78,7 @@
>  
>  
>  /* Graphics reset regs */
> -#define I965_GDRST 0xc0 /* PCI config register */
> +#define I915_GDRST 0xc0 /* PCI config register */
>  #define  GRDOM_FULL	(0<<2)
>  #define  GRDOM_RENDER	(1<<2)
>  #define  GRDOM_MEDIA	(3<<2)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 6516fa1..54f8265 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1345,27 +1345,27 @@ int i915_get_reset_stats_ioctl(struct drm_device *dev,
>  	return 0;
>  }
>  
> -static int i965_reset_complete(struct drm_device *dev)
> +static int i915_reset_complete(struct drm_device *dev)
>  {
>  	u8 gdrst;
> -	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
> +	pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
>  	return (gdrst & GRDOM_RESET_STATUS) == 0;
>  }
>  
> -static int i965_do_reset(struct drm_device *dev)
> +static int i915_do_reset(struct drm_device *dev)
>  {
>  	/* assert reset for at least 20 usec */
> -	pci_write_config_byte(dev->pdev, I965_GDRST, GRDOM_RESET_ENABLE);
> +	pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
>  	udelay(20);
> -	pci_write_config_byte(dev->pdev, I965_GDRST, 0);
> +	pci_write_config_byte(dev->pdev, I915_GDRST, 0);
>  
> -	return wait_for(i965_reset_complete(dev), 500);
> +	return wait_for(i915_reset_complete(dev), 500);
>  }
>  
>  static int g4x_reset_complete(struct drm_device *dev)
>  {
>  	u8 gdrst;
> -	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
> +	pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
>  	return (gdrst & GRDOM_RESET_ENABLE) == 0;
>  }
>  
> @@ -1374,7 +1374,7 @@ static int g4x_do_reset(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int ret;
>  
> -	pci_write_config_byte(dev->pdev, I965_GDRST,
> +	pci_write_config_byte(dev->pdev, I915_GDRST,
>  			      GRDOM_RENDER | GRDOM_RESET_ENABLE);
>  	ret =  wait_for(g4x_reset_complete(dev), 500);
>  	if (ret)
> @@ -1384,7 +1384,7 @@ static int g4x_do_reset(struct drm_device *dev)
>  	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
>  	POSTING_READ(VDECCLK_GATE_D);
>  
> -	pci_write_config_byte(dev->pdev, I965_GDRST,
> +	pci_write_config_byte(dev->pdev, I915_GDRST,
>  			      GRDOM_MEDIA | GRDOM_RESET_ENABLE);
>  	ret =  wait_for(g4x_reset_complete(dev), 500);
>  	if (ret)
> @@ -1394,7 +1394,7 @@ static int g4x_do_reset(struct drm_device *dev)
>  	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
>  	POSTING_READ(VDECCLK_GATE_D);
>  
> -	pci_write_config_byte(dev->pdev, I965_GDRST, 0);
> +	pci_write_config_byte(dev->pdev, I915_GDRST, 0);
>  
>  	return 0;
>  }
> @@ -1452,8 +1452,8 @@ int intel_gpu_reset(struct drm_device *dev)
>  		return ironlake_do_reset(dev);
>  	else if (IS_G4X(dev))
>  		return g4x_do_reset(dev);
> -	else if (IS_GEN4(dev))
> -		return i965_do_reset(dev);
> +	else if (IS_GEN4(dev) || (IS_GEN3(dev) &&  !IS_G33(dev)))
> +		return i915_do_reset(dev);
>  	else
>  		return -ENODEV;
>  }
> -- 
> 2.0.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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