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From: Daniel Vetter <daniel@ffwll.ch>
To: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH v3 3/3] drm/i915:bxt: Enable Pooled EU support
Date: Tue, 21 Jul 2015 09:33:21 +0200	[thread overview]
Message-ID: <20150721073321.GU16722@phenom.ffwll.local> (raw)
In-Reply-To: <1437385571-24874-4-git-send-email-arun.siluvery@linux.intel.com>

On Mon, Jul 20, 2015 at 10:46:11AM +0100, Arun Siluvery wrote:
> This mode allows to assign EUs to pools which can process work collectively.
> The command to enable this mode should be issued as part of context initialization.
> 
> The pooled mode is global, once enabled it has to stay the same across all
> contexts until HW reset hence this is sent in auxiliary golden context batch.
> Thanks to Mika for the preliminary review and comments.
> 
> v2: explain why this is enabled in golden context, use feature flag while
> enabling the support (Chris)
> 
> v3: Pooled EU support announced in userspace before enabling in kernel,
> to simplify include all changes in the same patch.
> 
> User space clients need to know when the pooled EU feature is present
> and enabled on the hardware so that they can adapt work submissions.
> Create a new device info flag for this purpose, and create a new GETPARAM
> entry to allow user space to query its setting.

Where is this userspace? No concerns yet for backwards compat since bxt
isn't out of preliminary hw support. But to avoid that we need to patch
_all_ userspace out there (i.e. mesa, beignet, ddx, libva).

I merged the prep patches meanwhile.
-Daniel

> 
> Set has_pooled_eu to true in the Broxton static device info - Broxton
> supports the feature in hardware and the driver will enable it by
> default.
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Armin Reese <armin.c.reese@intel.com>
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c              |  3 +++
>  drivers/gpu/drm/i915/i915_drv.c              |  1 +
>  drivers/gpu/drm/i915/i915_drv.h              |  5 ++++-
>  drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  2 ++
>  include/uapi/drm/i915_drm.h                  |  1 +
>  6 files changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 5e63076..6c31beb 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -170,6 +170,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>  	case I915_PARAM_HAS_RESOURCE_STREAMER:
>  		value = HAS_RESOURCE_STREAMER(dev);
>  		break;
> +	case I915_PARAM_HAS_POOLED_EU:
> +		value = HAS_POOLED_EU(dev);
> +		break;
>  	default:
>  		DRM_DEBUG("Unknown parameter %d\n", param->param);
>  		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e44dc0d..213f74d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -389,6 +389,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.num_pipes = 3,
>  	.has_ddi = 1,
>  	.has_fbc = 1,
> +	.has_pooled_eu = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  };
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 768d1db..32850a8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -775,7 +775,8 @@ struct intel_csr {
>  	func(supports_tv) sep \
>  	func(has_llc) sep \
>  	func(has_ddi) sep \
> -	func(has_fpga_dbg)
> +	func(has_fpga_dbg) sep \
> +	func(has_pooled_eu)
>  
>  #define DEFINE_FLAG(name) u8 name:1
>  #define SEP_SEMICOLON ;
> @@ -2549,6 +2550,8 @@ struct drm_i915_cmd_table {
>  #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
>  				    INTEL_INFO(dev)->gen >= 8)
>  
> +#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
> +
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>  #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 5026a62..8866040 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -93,6 +93,7 @@ free_gem:
>  
>  static int render_state_setup(struct render_state *so)
>  {
> +	struct drm_device *dev = so->obj->base.dev;
>  	const struct intel_renderstate_rodata *rodata = so->rodata;
>  	unsigned int i = 0, reloc_index = 0;
>  	struct page *page;
> @@ -134,6 +135,18 @@ static int render_state_setup(struct render_state *so)
>  
>  	so->aux_batch_offset = i * sizeof(u32);
>  
> +	if (HAS_POOLED_EU(dev)) {
> +		u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ?
> +				   0x00777000 : 0);
> +
> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
> +		OUT_BATCH(d, i, pool_config);
> +		OUT_BATCH(d, i, 0);
> +		OUT_BATCH(d, i, 0);
> +		OUT_BATCH(d, i, 0);
> +	}
> +
>  	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
>  	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9a2ffad..e052499 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -379,6 +379,8 @@
>   */
>  #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
>  
> +#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
> +#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
>  #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
>  #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
>  #define   SC_UPDATE_SCISSOR       (0x1<<1)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index e7c29f1..9649577 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -356,6 +356,7 @@ typedef struct drm_i915_irq_wait {
>  #define I915_PARAM_EU_TOTAL		 34
>  #define I915_PARAM_HAS_GPU_RESET	 35
>  #define I915_PARAM_HAS_RESOURCE_STREAMER 36
> +#define I915_PARAM_HAS_POOLED_EU         37
>  
>  typedef struct drm_i915_getparam {
>  	int param;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-07-21  7:30 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-20  9:46 [PATCH v3 0/3] Add Pooled EU support to BXT Arun Siluvery
2015-07-20  9:46 ` [PATCH v3 1/3] drm/i915: Do kunmap if renderstate parsing fails Arun Siluvery
2015-07-20  9:46 ` [PATCH v3 2/3] drm/i915: Add provision to extend Golden context batch Arun Siluvery
2015-07-20  9:46 ` [PATCH v3 3/3] drm/i915:bxt: Enable Pooled EU support Arun Siluvery
2015-07-21  7:33   ` Daniel Vetter [this message]
  -- strict thread matches above, loose matches on Subject: below --
2015-07-17 18:13 [PATCH v2 4/4] " Arun Siluvery
2015-07-17 18:55 ` [PATCH v3 3/3] " Arun Siluvery

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