From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
intel-gfx@lists.freedesktop.org, Len Brown <lenb@kernel.org>
Subject: Re: [PATCH] RFC drm/i915: Emulate 64bit registers for residency counters
Date: Thu, 7 Apr 2016 17:17:52 +0300 [thread overview]
Message-ID: <20160407141752.GL4329@intel.com> (raw)
In-Reply-To: <20160407135801.GD18061@nuc-i3427.alporthouse.com>
On Thu, Apr 07, 2016 at 02:58:01PM +0100, Chris Wilson wrote:
> On Thu, Apr 07, 2016 at 04:18:16PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 07, 2016 at 01:59:44PM +0100, Chris Wilson wrote:
> > > Can we set that bit ourselves? That puts the overflow into the 1 hour
> > > mark. Thanks,
> >
> > I don't know if it's safe to frob the bit. I worry that something
> > outside our control might depend on it staying put.
>
> A quick frob of the bit says that it is RO. When I try to set it, it
> doesn't stick. :(
Same here on my VLV. I was able to toggle it on my BSW. Perhaps
something can lock it down, and my BSW BIOS just doesn't do that.
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-04-07 14:17 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-07 11:24 [PATCH] RFC drm/i915: Emulate 64bit registers for residency counters Chris Wilson
2016-04-07 12:13 ` Ville Syrjälä
2016-04-07 12:37 ` Chris Wilson
2016-04-07 12:49 ` Ville Syrjälä
2016-04-07 12:59 ` Chris Wilson
2016-04-07 13:18 ` Ville Syrjälä
2016-04-07 13:58 ` Chris Wilson
2016-04-07 14:17 ` Ville Syrjälä [this message]
2016-04-07 15:29 ` ✗ Fi.CI.BAT: failure for " Patchwork
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