From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 17/18] drm/i915: Add cxsr toggle tracepoint
Date: Thu, 16 Feb 2017 20:07:50 +0200 [thread overview]
Message-ID: <20170216180751.3097-18-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20170216180751.3097-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a tracepoint for observing changes in the cxsr state. The tracepoint
will dump out the frame and scanline counters for each pipe so that the
information can be compared with eg. plane update tracepoints.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_trace.h | 30 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 865084fd8455..bca46406030d 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -16,6 +16,36 @@
/* watermark/fifo updates */
+TRACE_EVENT(intel_memory_cxsr,
+ TP_PROTO(struct drm_i915_private *dev_priv, bool old, bool new),
+ TP_ARGS(dev_priv, old, new),
+
+ TP_STRUCT__entry(
+ __array(u32, frame, 3)
+ __array(u32, scanline, 3)
+ __field(bool, old)
+ __field(bool, new)
+ ),
+
+ TP_fast_assign(
+ enum pipe pipe;
+ for_each_pipe(dev_priv, pipe) {
+ __entry->frame[pipe] =
+ dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe);
+ __entry->scanline[pipe] =
+ intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe));
+ }
+ __entry->old = old;
+ __entry->new = new;
+ ),
+
+ TP_printk("%s->%s, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
+ onoff(__entry->old), onoff(__entry->new),
+ __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
+ __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
+ __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
+);
+
TRACE_EVENT(vlv_wm,
TP_PROTO(struct intel_crtc *crtc, const struct vlv_wm_values *wm),
TP_ARGS(crtc, wm),
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 69b52da19f6d..0cba41d94863 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -367,6 +367,8 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
return false;
}
+ trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
+
DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
enableddisabled(enable),
enableddisabled(was_enabled));
--
2.10.2
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next prev parent reply other threads:[~2017-02-16 18:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-16 18:07 [PATCH v2 00/18] drm/i915: VLV/CHV two-stage watermarks (v2) ville.syrjala
2017-02-16 18:07 ` [PATCH 01/18] drm/i915: Track visible planes in a bitmask ville.syrjala
2017-02-16 18:07 ` [PATCH v2 02/18] drm/i915: Track plane fifo sizes under intel_crtc ville.syrjala
2017-02-16 18:07 ` [PATCH 03/18] drm/i915: Move vlv wms from crtc->wm_state to crtc->wm.active.vlv ville.syrjala
2017-02-16 18:07 ` [PATCH 04/18] drm/i915: Plop vlv wm state into crtc_state ville.syrjala
2017-02-16 18:07 ` [PATCH 05/18] drm/i915: Plop vlv/chv fifo sizes into crtc state ville.syrjala
2017-02-16 18:07 ` [PATCH 06/18] drm/i915: Compute VLV/CHV FIFO sizes based on the PM2 watermarks ville.syrjala
2017-02-16 18:07 ` [PATCH 07/18] drm/i915: Compute vlv/chv wms the atomic way ville.syrjala
2017-02-16 18:07 ` [PATCH 08/18] drm/i915: Skip useless watermark/FIFO related work on VLV/CHV when not needed ville.syrjala
2017-02-16 18:07 ` [PATCH 09/18] drm/i915: Compute proper intermediate wms for vlv/cvh ville.syrjala
2017-02-16 18:07 ` [PATCH 10/18] drm/i915: Nuke crtc->wm.cxsr_allowed ville.syrjala
2017-02-16 18:07 ` [PATCH 11/18] drm/i915: Only use update_wm_{pre, post} for pre-ilk platforms ville.syrjala
2017-02-16 18:07 ` [PATCH 12/18] drm/i915: Sanitize VLV/CHV watermarks properly ville.syrjala
2017-02-16 18:07 ` [PATCH 13/18] drm/i915: Workaround VLV/CHV sprite1->sprite0 enable underrun ville.syrjala
2017-02-16 18:07 ` [PATCH 14/18] drm/i915: Kill level 0 wm hack for VLV/CHV ville.syrjala
2017-02-16 18:07 ` [PATCH 15/18] drm/i915: Add plane update/disable tracepoints ville.syrjala
2017-02-16 18:07 ` [PATCH 16/18] drm/i915: Add VLV/CHV watermark/FIFO programming tracepoints ville.syrjala
2017-02-16 18:07 ` ville.syrjala [this message]
2017-02-16 18:07 ` [PATCH 18/18] drm/i915: Add FIFO underrun tracepoints ville.syrjala
2017-03-01 15:15 ` Maarten Lankhorst
2017-02-16 22:22 ` ✓ Fi.CI.BAT: success for drm/i915: VLV/CHV two-stage watermarks (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-03-02 17:14 [PATCH v3 00/18] drm/i915: VLV/CHV two-stage watermarks (v3) ville.syrjala
2017-03-02 17:15 ` [PATCH 17/18] drm/i915: Add cxsr toggle tracepoint ville.syrjala
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