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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: intel-gfx@lists.freedesktop.org, paulo.r.zanoni@intel.com,
	maarten.lankhorst@intel.com
Subject: Re: [PATCH v2 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode
Date: Thu, 29 Jun 2017 20:36:53 +0300	[thread overview]
Message-ID: <20170629173653.GD12629@intel.com> (raw)
In-Reply-To: <20170629164030.12837-2-mahesh1.kumar@intel.com>

On Thu, Jun 29, 2017 at 10:10:29PM +0530, Mahesh Kumar wrote:
> In Gen9 platform Interlaced fetch mode doesn't support following plane
> configuration:
>  - Y/Yf tiling
>  - 90/270 rotation
>  - YUV420 hybrid planar source pixel formats.
> 
> This patch adds check to fail the flip if any of the above configuration
> is requested.
> 
> Changes since V1:
>  - handle checks in intel_plane_atomic_check_with_state (ville)
>  - takeout plane scaler checks, combine with pipe scaler in next patch
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 33 +++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 4325cb0a04f5..2b60a67c5393 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -114,6 +114,8 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
>  	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct drm_plane_state *state = &intel_state->base;
>  	struct intel_plane *intel_plane = to_intel_plane(plane);
> +	const struct drm_display_mode *adjusted_mode =
> +						&crtc_state->base.adjusted_mode;

Indentation is off in several places. Pls fix your editor.

>  	int ret;
>  
>  	/*
> @@ -173,6 +175,37 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> +	/*
> +	 * Y-tiling is not supported in IF-ID Interlace mode in
> +	 * GEN9 and above.
> +	 * Scaling is not supported with Interlaced fetch mode.
> +	 * YUV420 hybrid planar source pixel formats are not supported with
> +	 * Interlaced fetch mode.
> +	 */
> +	if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
> +			adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +		struct drm_framebuffer *fb = state->fb;
> +		struct drm_format_name_buf format_name;
> +
> +		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> +		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
> +			DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> +			return -EINVAL;
> +		}
> +
> +		switch (fb->format->format) {
> +		case DRM_FORMAT_NV12:
> +		case DRM_FORMAT_YUV420:
> +		case DRM_FORMAT_YVU420:

Non-NV12 should be dropped, but actually I think you can drop this check
entirely since skl_update_scaler() will already reject NV12 since
that always needs a scaler.

> +			DRM_DEBUG_KMS("Unsupported pixel format %s for IF-ID\n",
> +				      drm_get_format_name(fb->format->format,
> +				      &format_name));
> +			return -EINVAL;
> +		default:
> +			break;
> +		}
> +	}
> +
>  	/* FIXME pre-g4x don't work like this */
>  	if (intel_state->base.visible)
>  		crtc_state->active_planes |= BIT(intel_plane->id);
> -- 
> 2.13.0

-- 
Ville Syrjälä
Intel OTC
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Intel-gfx mailing list
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  reply	other threads:[~2017-06-29 17:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-29 16:40 [PATCH v2 0/2] Handle unsupported configuration with IF-ID Mahesh Kumar
2017-06-29 16:40 ` [PATCH v2 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode Mahesh Kumar
2017-06-29 17:36   ` Ville Syrjälä [this message]
2017-06-29 16:40 ` [PATCH v2 2/2] drm/i915/skl+: Scaling not supported in IF-ID " Mahesh Kumar
2017-06-29 17:37   ` Ville Syrjälä
2017-06-29 16:58 ` ✗ Fi.CI.BAT: warning for Handle unsupported configuration with IF-ID (rev2) Patchwork

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