Re: [PATCH v2 1/3] drm/i915: Fix up CNL cdclk related limits

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Jul 10, 2017 at 05:34:11PM +0000, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Mon, 2017-07-10 at 16:02 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Follow the GLK path when computing cdclk and related limits. CNL
> > pipes also produce two pixels per clock, so that's what we should
> > really use. However for the purposes of pixel rate calculations we
> > will assume one pixel per clock to keep the voltage higher, at least
> > until the missing voltage scaling for DDI clocks is implemented.
> > 
> 
> Does the lack of  correct voltage scaling implementation affect only
> intel_compute_max_dotclk()? i.e., allowing a pixel rate of
> 2*max_cdclk_freq? Or does it mean cnl_calc_cdclk() cannot take into
> account pixel_rate <= 2*cdclk_freq for any frequency?
> 
> 
> With this patch, 
> bdw_adjust_min_pipe_pixel_rate() compares pixel_rate to 2*cdclk
> cnl_calc_cdclk() compares pixel_rate to 1*cdclk.
> Isn't that a discrepancy?

Hmm. Yeah. I suppose I should just squash this with patch 2/3. My
original intention for this separate patch was to respect the 2x
limit rather than the 1x limit. But since we couldn't do that I
suppose the justification for this patch has pretty much gone
away, and as you point out, it just leads to a mess.

The combination of patches 1/3+2/3 should still do the right thing
because we no longer use the pixel rate in the audio workarounds.

> 
> 
> > For the HBR2 vs. audio issue the limit should more correctly be 336
> > MHz, but the GLK limit of 316.8 MHz works just as well and results
> > in picking at least 336 MHz. Also toss in some related w/a numbers.
> 
> In this case, _adjust_min_pipe_pixel_rate() will return pixel_rate as
> 633.6 MHz, followed by cnl_calc_cdclk() returning 528 MHz cdclk. But,
> isn't the correct workaround cdclk 336 MHz?
> 
> 
> > 
> > v2: Assume 1 pixel per clock for the purposes of max pixel rate
> >     calculation until DDI clock voltage scaling is handled
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 20 ++++++++++++++------
> >  1 file changed, 14 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 1241e5891b29..4b8eb6a7d852 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1752,12 +1752,13 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >  	    crtc_state->has_audio &&
> >  	    crtc_state->port_clock >= 540000 &&
> >  	    crtc_state->lane_count == 4) {
> > -		if (IS_CANNONLAKE(dev_priv))
> > -			pixel_rate = max(316800, pixel_rate);
> > -		else if (IS_GEMINILAKE(dev_priv))
> > +		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> > +			/* Display WA #1145: glk,cnl */
> >  			pixel_rate = max(2 * 316800, pixel_rate);
> > -		else
> > +		} else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
> > +			/* Display WA #1144: skl,bxt */
> >  			pixel_rate = max(432000, pixel_rate);
> > +		}
> >  	}
> >  
> >  	/* According to BSpec, "The CD clock frequency must be at least twice
> > @@ -1766,7 +1767,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >  	 * two pixels per clock.
> >  	 */
> >  	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> > -		if (IS_GEMINILAKE(dev_priv))
> > +		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> >  			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> >  		else
> >  			pixel_rate = max(2 * 96000, pixel_rate);
> > @@ -1999,7 +2000,14 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> >  {
> >  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >  
> > -	if (IS_GEMINILAKE(dev_priv))
> > +	if (INTEL_GEN(dev_priv) >= 10)
> > +		/*
> > +		 * FIXME: Allow '2 * max_cdclk_freq'
> > +		 * once DDI clock voltage requirements are
> > +		 * handled correctly.
> > +		 */
> > +		return max_cdclk_freq;
> > +	else if (IS_GEMINILAKE(dev_priv))
> >  		/*
> >  		 * FIXME: Limiting to 99% as a temporary workaround. See
> >  		 * glk_calc_cdclk() for details.

-- 
Ville Syrjälä
Intel OTC
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