Re: [PATCH 1/1] drm/i915/cnl: Extend HDMI 2.0 support to CNL.

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Sat, Nov 11, 2017 at 09:47:40AM +0000, Sharma, Shashank wrote:
> I am still waiting for the dmesg logs, Rodrigo :P
> 
> I am pretty sure that you would have picked up if there is a general
> problem, wit the modeset or HDMI.

yep... my bad... sorry...
We will provide that soon.

> 
> I just want to check what is following from the mode and monitor combination
> during blankout:
> 
> - is the mode YCBCR420 ?
> 
> - is scrambling enabled ?
> 
> - does the monitor supports 4k@60 RGB (594Mhz) or its 4k@60 YCBCR420
> (300Mhz)
> 
> - are we in 12 BPC deep color mode ?
> - is this a CEA 4k@60 mode, or other one ?
> 
> Regards
> Shashank
> On 11/11/2017 5:34 AM, Rodrigo Vivi wrote:
> > On Fri, Nov 10, 2017 at 11:50:21PM +0000, Manasi Navare wrote:
> > > Looks good.
> > > But are these the only places that need change to support 2.0?
> > > Dont we need any changes in voltage swing programming or DDI clocks?
> > not that I'm aware of... but that would explain the blank screens...
> > 
> > > Manasi`
> > > 
> > > On Fri, Nov 10, 2017 at 02:26:26PM -0800, Rodrigo Vivi wrote:
> > > > Starting on GLK we support HDMI 2.0. So this patch only
> > > > extend the work Shashank has made to GLK to CNL.
> > > > 
> > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > >   drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++---
> > > >   1 file changed, 4 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > index 2d95db64cdf2..1b22b587e98c 100644
> > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > @@ -1235,7 +1235,7 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
> > > >   		&dev_priv->vbt.ddi_port_info[encoder->port];
> > > >   	int max_tmds_clock;
> > > > -	if (IS_GEMINILAKE(dev_priv))
> > > > +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> > > >   		max_tmds_clock = 594000;
> > > >   	else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> > > >   		max_tmds_clock = 300000;
> > > > @@ -1511,7 +1511,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> > > >   	pipe_config->lane_count = 4;
> > > > -	if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
> > > > +	if (scdc->scrambling.supported && (IS_GEMINILAKE(dev_priv) ||
> > > > +					   INTEL_GEN(dev_priv) >= 10) {
> > > >   		if (scdc->scrambling.low_rates)
> > > >   			pipe_config->hdmi_scrambling = true;
> > > > @@ -2033,7 +2034,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> > > >   	connector->doublescan_allowed = 0;
> > > >   	connector->stereo_allowed = 1;
> > > > -	if (IS_GEMINILAKE(dev_priv))
> > > > +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> > > >   		connector->ycbcr_420_allowed = true;
> > > >   	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
> > > > -- 
> > > > 2.13.6
> > > > 
> 
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