Re: [PATCH 2/2] drm/i915: Wait for gen3 reset status to be asserted

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Feb 07, 2018 at 10:08:45AM +0000, Chris Wilson wrote:
> After we assert the reset request (and wait for 20us), when the device
> has been fully reset it asserts the reset-status bit. Before we stop
> requesting the reset and allow the device to return to normal, we should
> wait for the reset to be completed. (Similar to how we wait for the
> device to return to normal after deasserting the reset request.)
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 612aad205b59..dd86428774da 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1555,19 +1555,27 @@ static bool i915_reset_complete(struct pci_dev *pdev)
>  	u8 gdrst;
>  
>  	pci_read_config_byte(pdev, I915_GDRST, &gdrst);
> -	return (gdrst & GRDOM_RESET_STATUS) == 0;
> +	return gdrst & GRDOM_RESET_STATUS;
>  }
>  
>  static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
>  {
>  	struct pci_dev *pdev = dev_priv->drm.pdev;
> +	int err;
>  
>  	/* assert reset for at least 20 usec */
>  	pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
>  	usleep_range(50, 200);
> +
> +	err = wait_for(i915_reset_complete(pdev), 500);

The hardware should indicate that it's in reset as long as we keep the
reset asserted. So this looks like an obfuscated usleep(500) to me.
Did you mean !reset_complete?

> +
>  	pci_write_config_byte(pdev, I915_GDRST, 0);
> +	usleep_range(50, 200);
> +
> +	if (!err)
> +		err = wait_for(!i915_reset_complete(pdev), 500);
>  
> -	return wait_for(i915_reset_complete(pdev), 500);
> +	return err;
>  }
>  
>  static bool g4x_reset_complete(struct pci_dev *pdev)
> -- 
> 2.16.1

-- 
Ville Syrjälä
Intel OTC
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