From: Tvrtko Ursulin <tursulin@ursulin.net>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/6] drm/i915/pmu: Fix enable count array size and bounds checking
Date: Mon, 12 Feb 2018 18:57:35 +0000 [thread overview]
Message-ID: <20180212185740.4429-2-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20180212185740.4429-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Enable count array is supposed to have one counter for each possible
engine sampler. As such array sizing and bounds checking is not
correct when more engine samplers are added.
At the same time tidy the assert for readability and robustness.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries")
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_pmu.c | 13 +++++++++----
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 964467b03e4d..a0ae7ca220fd 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -576,7 +576,8 @@ static void i915_pmu_enable(struct perf_event *event)
* Update the bitmask of enabled events and increment
* the event reference counter.
*/
- GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
+ BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS);
+ GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
i915->pmu.enable |= BIT_ULL(bit);
i915->pmu.enable_count[bit]++;
@@ -600,7 +601,10 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(!engine);
engine->pmu.enable |= BIT(sample);
- GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
+ BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
+ (1 << I915_PMU_SAMPLE_BITS));
+ GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
+ GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
engine->pmu.enable_count[sample]++;
}
@@ -632,7 +636,8 @@ static void i915_pmu_disable(struct perf_event *event)
engine_event_class(event),
engine_event_instance(event));
GEM_BUG_ON(!engine);
- GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
+ GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
+ GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
/*
* Decrement the reference count and clear the enabled
@@ -642,7 +647,7 @@ static void i915_pmu_disable(struct perf_event *event)
engine->pmu.enable &= ~BIT(sample);
}
- GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
+ GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
/*
* Decrement the reference count and clear the enabled
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8f1a4badf812..3e98a589716a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -363,7 +363,7 @@ struct intel_engine_cs {
*
* Index number corresponds to the bit number from @enable.
*/
- unsigned int enable_count[I915_PMU_SAMPLE_BITS];
+ unsigned int enable_count[1 << I915_PMU_SAMPLE_BITS];
/**
* @sample: Counter values for sampling events.
*
--
2.14.1
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next prev parent reply other threads:[~2018-02-12 18:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-12 18:57 [PATCH v3 0/6] Queued/runnable/running engine stats Tvrtko Ursulin
2018-02-12 18:57 ` Tvrtko Ursulin [this message]
2018-02-12 18:57 ` [PATCH 2/6] drm/i915: Keep a count of requests waiting for a slot on GPU Tvrtko Ursulin
2018-02-12 18:57 ` [PATCH 3/6] drm/i915: Keep a count of requests submitted from userspace Tvrtko Ursulin
2018-02-12 18:57 ` [PATCH 4/6] drm/i915/pmu: Add queued counter Tvrtko Ursulin
2018-02-12 18:57 ` [PATCH 5/6] drm/i915/pmu: Add runnable counter Tvrtko Ursulin
2018-02-12 18:57 ` [PATCH 6/6] drm/i915/pmu: Add running counter Tvrtko Ursulin
2018-02-12 19:20 ` ✓ Fi.CI.BAT: success for Queued/runnable/running engine stats (rev2) Patchwork
2018-02-12 22:57 ` ✗ Fi.CI.IGT: failure " Patchwork
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