public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler
Date: Thu, 15 Feb 2018 07:37:13 +0000	[thread overview]
Message-ID: <20180215073713.26985-2-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20180215073713.26985-1-chris@chris-wilson.co.uk>

The compiler is not automatically caching the i915->regs address inside
a register and emitting a load for every mmio access. For simple
functions like gen8_gt_irq_handler that are already using the raw
accessors, we can open-code them for substantial savings:

add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-83 (-83)
Function                                     old     new   delta
gen8_gt_irq_handler                          290     266     -24
gen8_gt_irq_ack                              181     122     -59
Total: Before=954637, After=954554, chg -0.01%

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
And so begins the long haul of de-I915_READ/WRITE-ing the driver...
---
 drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++----------------------
 1 file changed, 27 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b7b377ba7b6e..10d62b33cb13 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1413,9 +1413,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
 		tasklet_hi_schedule(&execlists->tasklet);
 }
 
-static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_ack(struct drm_i915_private *i915,
 			    u32 master_ctl, u32 gt_iir[4])
 {
+	void __iomem * const regs = i915->regs;
+
 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
 		      GEN8_GT_BCS_IRQ | \
 		      GEN8_GT_VCS1_IRQ | \
@@ -1425,62 +1427,57 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
 		      GEN8_GT_GUC_IRQ)
 
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-		gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
-		if (gt_iir[0])
-			I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
+		gt_iir[0] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
+		if (likely(gt_iir[0]))
+			writel(gt_iir[0], regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
 	}
 
 	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
-		gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
-		if (gt_iir[1])
-			I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
+		gt_iir[1] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(1)));
+		if (likely(gt_iir[1]))
+			writel(gt_iir[1], regs + i915_mmio_reg_offset(GEN8_GT_IIR(1)));
 	}
 
-	if (master_ctl & GEN8_GT_VECS_IRQ) {
-		gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
-		if (gt_iir[3])
-			I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
+	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
+		gt_iir[2] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(2)));
+		if (likely(gt_iir[2] & (i915->pm_rps_events | i915->pm_guc_events)))
+			writel(gt_iir[2] & (i915->pm_rps_events |
+					    i915->pm_guc_events),
+			       regs + i915_mmio_reg_offset(GEN8_GT_IIR(2)));
 	}
 
-	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
-		gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
-		if (gt_iir[2] & (dev_priv->pm_rps_events |
-				 dev_priv->pm_guc_events)) {
-			I915_WRITE_FW(GEN8_GT_IIR(2),
-				      gt_iir[2] & (dev_priv->pm_rps_events |
-						   dev_priv->pm_guc_events));
-		}
+	if (master_ctl & GEN8_GT_VECS_IRQ) {
+		gt_iir[3] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(3)));
+		if (likely(gt_iir[3]))
+			writel(gt_iir[3], regs + i915_mmio_reg_offset(GEN8_GT_IIR(3)));
 	}
 }
 
-static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_handler(struct drm_i915_private *i915,
 				u32 master_ctl, u32 gt_iir[4])
 {
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-		gen8_cs_irq_handler(dev_priv->engine[RCS],
+		gen8_cs_irq_handler(i915->engine[RCS],
 				    gt_iir[0], GEN8_RCS_IRQ_SHIFT);
-		gen8_cs_irq_handler(dev_priv->engine[BCS],
+		gen8_cs_irq_handler(i915->engine[BCS],
 				    gt_iir[0], GEN8_BCS_IRQ_SHIFT);
 	}
 
 	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
-		gen8_cs_irq_handler(dev_priv->engine[VCS],
+		gen8_cs_irq_handler(i915->engine[VCS],
 				    gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
-		gen8_cs_irq_handler(dev_priv->engine[VCS2],
+		gen8_cs_irq_handler(i915->engine[VCS2],
 				    gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
 	}
 
 	if (master_ctl & GEN8_GT_VECS_IRQ) {
-		gen8_cs_irq_handler(dev_priv->engine[VECS],
+		gen8_cs_irq_handler(i915->engine[VECS],
 				    gt_iir[3], GEN8_VECS_IRQ_SHIFT);
 	}
 
 	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
-		if (gt_iir[2] & dev_priv->pm_rps_events)
-			gen6_rps_irq_handler(dev_priv, gt_iir[2]);
-
-		if (gt_iir[2] & dev_priv->pm_guc_events)
-			gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+		gen6_rps_irq_handler(i915, gt_iir[2]);
+		gen9_guc_irq_handler(i915, gt_iir[2]);
 	}
 }
 
-- 
2.16.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-02-15  7:37 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-15  7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
2018-02-15  7:37 ` Chris Wilson [this message]
2018-02-15 16:57   ` [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler Chris Wilson
2018-02-15 17:04     ` Mika Kuoppala
2018-02-19 10:09   ` [PATCH v2] " Chris Wilson
2018-02-19 13:59     ` Mika Kuoppala
2018-02-19 14:12       ` Chris Wilson
2018-02-15  7:58 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir Patchwork
2018-02-15  8:14 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-15 13:31 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-15 15:21 ` [PATCH 1/2] " Mika Kuoppala
2018-02-15 16:00   ` Chris Wilson
2018-02-15 18:35     ` Ville Syrjälä
2018-02-19 10:31 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2) Patchwork
2018-02-19 11:41 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-19 15:51   ` Chris Wilson
2018-02-19 13:47 ` [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Mika Kuoppala

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180215073713.26985-2-chris@chris-wilson.co.uk \
    --to=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox