From: Jeff McGee <jeff.mcgee@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: kalyan.kondapally@intel.com, ben@bwidawsk.net
Subject: Re: [RFC 7/8] drm/i915: Skip CSB processing on invalid CSB tail
Date: Wed, 21 Mar 2018 10:31:45 -0700 [thread overview]
Message-ID: <20180321173145.GD19343@jeffdesk> (raw)
In-Reply-To: <20180321172625.6415-8-jeff.mcgee@intel.com>
On Wed, Mar 21, 2018 at 10:26:24AM -0700, jeff.mcgee@intel.com wrote:
> From: Jeff McGee <jeff.mcgee@intel.com>
>
> Engine reset is fast. A context switch interrupt may be generated just
> prior to the reset such that the top half handler is racing with reset
> post-processing. The handler may set the irq_posted bit again after
> the reset code has cleared it to start fresh. Then the re-enabled
> tasklet will read the CSB head and tail from MMIO, which will be at
> the hardware reset values of 0 and 7 respectively, given that no
> actual CSB event has occurred since the reset. Mayhem then ensues as
> the tasklet starts processing invalid CSB entries.
>
> We can handle this corner case without adding any new synchronization
> between the irq top half and the reset work item. The tasklet can
> just skip CSB processing if the tail is not sane.
>
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> ---
If I drop this patch and substitute https://patchwork.freedesktop.org/patch/211831/
I will see irq_posted get set after reset which causes the first tasklet
run to re-process a previous CSB event and hit GEM_BUG_ON that nothing
was active.
-Jeff
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next prev parent reply other threads:[~2018-03-21 17:46 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-21 17:26 [RFC 0/8] Force preemption jeff.mcgee
2018-03-21 17:26 ` [RFC 1/8] drm/i915/execlists: Refactor out complete_preempt_context() jeff.mcgee
2018-03-21 17:26 ` [RFC 2/8] drm/i915: Add control flags to i915_handle_error() jeff.mcgee
2018-03-21 17:26 ` [RFC 3/8] drm/i915: Move engine reset prepare/finish to backends jeff.mcgee
2018-03-21 17:26 ` [RFC 4/8] drm/i915: Split execlists/guc reset prepartions jeff.mcgee
2018-03-21 17:26 ` [RFC 5/8] drm/i915/execlists: Flush pending preemption events during reset jeff.mcgee
2018-03-21 17:26 ` [RFC 6/8] drm/i915: Fix loop on CSB processing jeff.mcgee
2018-03-21 17:33 ` Jeff McGee
2018-03-21 18:06 ` Chris Wilson
2018-03-21 18:29 ` Jeff McGee
2018-03-21 19:04 ` Chris Wilson
2018-03-21 17:26 ` [RFC 7/8] drm/i915: Skip CSB processing on invalid CSB tail jeff.mcgee
2018-03-21 17:31 ` Jeff McGee [this message]
2018-03-21 18:12 ` Chris Wilson
2018-03-21 19:06 ` Chris Wilson
2018-03-21 17:26 ` [RFC 8/8] drm/i915: Force preemption to complete via engine reset jeff.mcgee
2018-03-21 18:50 ` ✗ Fi.CI.BAT: failure for Force preemption (rev2) Patchwork
2018-03-22 9:22 ` [RFC 0/8] Force preemption Tvrtko Ursulin
2018-03-22 9:28 ` Chris Wilson
2018-03-22 14:34 ` Jeff McGee
2018-03-22 15:35 ` Chris Wilson
2018-03-22 15:44 ` Jeff McGee
2018-03-22 15:57 ` Tvrtko Ursulin
2018-03-22 16:01 ` Jeff McGee
2018-03-22 17:41 ` Tvrtko Ursulin
2018-03-22 19:08 ` Jeff McGee
2018-03-22 19:59 ` Bloomfield, Jon
2018-03-23 13:20 ` Joonas Lahtinen
2018-03-23 13:37 ` Chris Wilson
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