Re: [PATCH] drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [PATCH] drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.
Date: Tue, 1 May 2018 17:23:10 -0700	[thread overview]
Message-ID: <20180502002310.GT3617@intel.com> (raw)
In-Reply-To: <20180501005722.6231-1-rodrigo.vivi@intel.com>

Please fully ignore this patch.

On Mon, Apr 30, 2018 at 05:57:22PM -0700, Rodrigo Vivi wrote:
> I believe I finally got the platform/panel that WA1183
> was targeting.
> 
> WA 1183 aims to fix the cdclk change for
> "CD clock frequency 308.57 or 617.14 MHz"
> 
> I faced one case here where the desired CDCLK to 308571 kHz,
> VCO 8640000 kHz doesn't stick, unless that we unconditionally
> disables and re-enables dpll0 and fully apply WA 1183.
> 
> [   42.857519] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 308571 kHz, VCO 8640000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
> [   42.897269] cdclk state doesn't match!
> [   42.901052] WARNING: CPU: 5 PID: 1116 at drivers/gpu/drm/i915/intel_cdclk.c:2084 intel_set_cdclk+0x5d/0x110 [i915]
> [   42.938004] RIP: 0010:intel_set_cdclk+0x5d/0x110 [i915]
> [   43.155253] WARNING: CPU: 5 PID: 1116 at drivers/gpu/drm/i915/intel_cdclk.c:2084 intel_set_cdclk+0x5d/0x110 [i915]
> [   43.170277] [drm:intel_dump_cdclk_state [i915]] [hw state] 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
> [   43.182566] [drm:intel_dump_cdclk_state [i915]] [sw state] 308571 kHz, VCO 8640000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
> 
> Fixes: 53421c2fe99c ("drm/i915: Apply Display WA #1183 on skl, kbl, and cfl")
> Cc: Arthur J Runyan" <arthur.j.runyan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 17 ++++++-----------
>  1 file changed, 6 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 32d24c69da3c..5a65a79965cd 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1026,26 +1026,21 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	if (dev_priv->cdclk.hw.vco != 0 &&
> -	    dev_priv->cdclk.hw.vco != vco)
> -		skl_dpll0_disable(dev_priv);
> +	skl_dpll0_disable(dev_priv);
>  
>  	cdclk_ctl = I915_READ(CDCLK_CTL);
>  
> -	if (dev_priv->cdclk.hw.vco != vco) {
> -		/* Wa Display #1183: skl,kbl,cfl */
> -		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> -		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> -		I915_WRITE(CDCLK_CTL, cdclk_ctl);
> -	}
> +	/* Wa Display #1183: skl,kbl,cfl */
> +	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> +	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> +	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>  
>  	/* Wa Display #1183: skl,kbl,cfl */
>  	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
>  	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>  	POSTING_READ(CDCLK_CTL);
>  
> -	if (dev_priv->cdclk.hw.vco != vco)
> -		skl_dpll0_enable(dev_priv, vco);
> +	skl_dpll0_enable(dev_priv, vco);
>  
>  	/* Wa Display #1183: skl,kbl,cfl */
>  	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> -- 
> 2.13.6
> 
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