Re: [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Jul 13, 2018 at 08:42:11AM -0700, Lucas De Marchi wrote:
> Instead of defining all registers twice, define just a PCH_GPIO_BASE
> that has the same address as PCH_GPIO_A and use that to calculate all
> the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> the same thing.
> 
> v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
>     macro to return a particular gpio address and move the enum out of
>     i915_reg.h (suggested by Jani)
> 
> v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
>     actually need to be changed (suggested by Daniel/Ville)
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h     |  3 ++-
>  drivers/gpu/drm/i915/i915_reg.h     | 24 +++++-------------------
>  drivers/gpu/drm/i915/intel_drv.h    | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_i2c.c    | 12 ++++--------
>  5 files changed, 28 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 7a58ca555197..ecff866bbbf1 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  
>  	MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>  		gmbus_mmio_write);
> -	MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> +	MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);

I have no idea of gpio_mmio_base is populated correctly at this point
for gvt, and I'm too lazy to find out.

>  	MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>  
>  	MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b31d48cf7a69..596e734a874f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1611,7 +1611,8 @@ struct drm_i915_private {
>  	struct mutex gmbus_mutex;
>  
>  	/**
> -	 * Base address of the gmbus and gpio block.
> +	 * Base address of where the gmbus and gpio blocks are located (either
> +	 * on PCH or on SoC for platforms without PCH).
>  	 */
>  	uint32_t gpio_mmio_base;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1f222af0324d..5e3ba9898f4e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3089,18 +3089,9 @@ enum i915_power_well_id {
>  /*
>   * GPIO regs
>   */
> -#define GPIOA			_MMIO(0x5010)
> -#define GPIOB			_MMIO(0x5014)
> -#define GPIOC			_MMIO(0x5018)
> -#define GPIOD			_MMIO(0x501c)
> -#define GPIOE			_MMIO(0x5020)
> -#define GPIOF			_MMIO(0x5024)
> -#define GPIOG			_MMIO(0x5028)
> -#define GPIOH			_MMIO(0x502c)
> -#define GPIOJ			_MMIO(0x5034)
> -#define GPIOK			_MMIO(0x5038)
> -#define GPIOL			_MMIO(0x503C)
> -#define GPIOM			_MMIO(0x5040)
> +#define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> +				      4 * (gpio))
> +
>  # define GPIO_CLOCK_DIR_MASK		(1 << 0)
>  # define GPIO_CLOCK_DIR_IN		(0 << 1)
>  # define GPIO_CLOCK_DIR_OUT		(1 << 1)
> @@ -7483,6 +7474,8 @@ enum {
>  
>  /* PCH */
>  
> +#define PCH_DISPLAY_BASE	0xc0000u
> +
>  /* south display engine interrupt: IBX */
>  #define SDE_AUDIO_POWER_D	(1 << 27)
>  #define SDE_AUDIO_POWER_C	(1 << 26)
> @@ -7671,13 +7664,6 @@ enum {
>  #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
>  #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
>  
> -#define PCH_GPIOA               _MMIO(0xc5010)
> -#define PCH_GPIOB               _MMIO(0xc5014)
> -#define PCH_GPIOC               _MMIO(0xc5018)
> -#define PCH_GPIOD               _MMIO(0xc501c)
> -#define PCH_GPIOE               _MMIO(0xc5020)
> -#define PCH_GPIOF               _MMIO(0xc5024)
> -
>  #define PCH_GMBUS0		_MMIO(0xc5100)
>  #define PCH_GMBUS1		_MMIO(0xc5104)
>  #define PCH_GMBUS2		_MMIO(0xc5108)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b09b6389a734..2d102f95b38e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -152,6 +152,22 @@
>   * Display related stuff
>   */
>  
> +enum i915_gpio {
> +	GPIOA = 0,

=0 not really needed

> +	GPIOB,
> +	GPIOC,
> +	GPIOD,
> +	GPIOE,
> +	GPIOF,
> +	GPIOG,
> +	GPIOH,
> +	__GPIOI_UNUSED,
> +	GPIOJ,
> +	GPIOK,
> +	GPIOL,
> +	GPIOM,
> +};

Weren't most things like this moved into intel_display.h a while back?

> +
>  /* store information about an Ixxx DVO */
>  /* The i830->i865 use multiple DVOs with multiple i2cs */
>  /* the i915, i945 have a single sDVO i2c bus - which is different */
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index bef32b7c248e..f03c7ca718b5 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -37,7 +37,7 @@
>  
>  struct gmbus_pin {
>  	const char *name;
> -	i915_reg_t reg;
> +	enum i915_gpio gpio;
>  };
>  
>  /* Map gmbus pin pairs to names and registers. */
> @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>  	else
>  		size = ARRAY_SIZE(gmbus_pins);
>  
> -	return pin < size &&
> -		i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> +	return pin < size && get_gmbus_pin(dev_priv, pin)->name;
>  }
>  
>  /* Intel GPIO access functions */
> @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
>  
>  	algo = &bus->bit_algo;
>  
> -	bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> -			      i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> +	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
>  	bus->adapter.algo_data = algo;
>  	algo->setsda = set_data;
>  	algo->setscl = set_clock;
> @@ -825,9 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>  	else if (!HAS_GMCH_DISPLAY(dev_priv))

I was slightly confused by this until I remeber that BXT uses the PCH
offsets for the south stuff even though it doesn't have a PCH. Might
want to add a comment here to unconfuse matter.

> -		dev_priv->gpio_mmio_base =
> -			i915_mmio_reg_offset(PCH_GPIOA) -
> -			i915_mmio_reg_offset(GPIOA);
> +		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
>  
>  	mutex_init(&dev_priv->gmbus_mutex);
>  	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> -- 
> 2.17.1

-- 
Ville Syrjälä
Intel
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