From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Flush chipset caches after GGTT writes
Date: Tue, 17 Jul 2018 08:13:41 -0700 [thread overview]
Message-ID: <20180717151339.GC7043@intel.com> (raw)
In-Reply-To: <153183823339.2136.15832732894667990634@skylake-alporthouse-com>
On Tue, Jul 17, 2018 at 03:37:13PM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-07-17 15:32:08)
> > On Tue, Jul 17, 2018 at 10:26:55AM +0100, Chris Wilson wrote:
> > > Our I915g (early gen3, the oldest machine we have in the farm) is still
> > > reporting occasional incoherency performing the following operations:
> > >
> > > 1) write through GGTT (indirect write into memory)
> > > 2) write through either CPU or WC (direct write into memory)
> > > 3) read from GGTT (indirect read)
> > >
> > > Instead of reporting the value from (2), the read from GGTT reports the
> > > earlier value written via the GGTT. We have made sure that the writes are
> > > flushed from the CPU (commit 3a32497f0dbe ("drm/i915/selftests: Provide
> > > full mb() around clflush") and commit add00e6d896f ("drm/i915: Flush the
> > > WCB following a WC write")), but still see the error, just less
> > > frequently. The only remaining cache that might be affected here is a
> > > chipset cache, so flush that as well.
> > >
> > > Testcase: igt/drv_selftest/live_coherency #gdg
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > ---
> > > drivers/gpu/drm/i915/i915_gem.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > index 42d24410a98c..08266791801e 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -802,7 +802,7 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
> > > * that was!).
> > > */
> > >
> > > - wmb();
> > > + i915_gem_chipset_flush(dev_priv);
> >
> > this seems a void change for me... because I couldn't find the implementation
> > of intel_gtt_chipset_flush() so it seems that we are just replacing wmb per wmb
>
> For gen3, it triggers a write into the igfx flush page via
> agp/intel-gtt.c, see i9xx_chipset_flush().
thanks for the pointer... now it makes sense
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-07-17 15:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 9:26 [PATCH] drm/i915: Flush chipset caches after GGTT writes Chris Wilson
2018-07-17 12:24 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-07-17 14:32 ` [PATCH] " Rodrigo Vivi
2018-07-17 14:37 ` Chris Wilson
2018-07-17 15:13 ` Rodrigo Vivi [this message]
2018-07-17 16:34 ` Chris Wilson
2018-07-17 15:01 ` ✓ Fi.CI.IGT: success for " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180717151339.GC7043@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox