Re: [Intel-gfx] [PATCH v8 2/2] drm/i915: Adding YUV444 packed format support for skl+

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Aug 30, 2018 at 04:40:27PM +0300, Stanislav Lisovskiy wrote:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
> 
> v2: Edited commit message, removed redundant whitespaces.
> 
> v3: Fixed fallthrough logic for the format switch cases.
> 
> v4: Yet again fixed fallthrough logic, to reuse code from other case
>     labels.
> 
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> 
> v6: Removed unneeded initializer for new XYUV format.
> 
> v7: Added scaling support for DRM_FORMAT_XYUV
> 
> v8: Edited commit message to be more clear about skl+, renamed
>     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
>     doesn't support per-pixel alpha. Fixed minor code issues.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 2 +-
>  drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
>  drivers/gpu/drm/i915/intel_sprite.c  | 1 +
>  3 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8534f88a60f6..e0c8480aaa02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6499,7 +6499,7 @@ enum {
>  #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
> -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
> +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
>  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
>  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 30fdfd1a3037..69ddecbcc224 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>  	DRM_FORMAT_YVYU,
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_XYUV,
>  };
>  
>  static const uint32_t skl_pri_planar_formats[] = {
> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
>  	DRM_FORMAT_YVYU,
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_XYUV,
>  	DRM_FORMAT_NV12,
>  };
>  
> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  		return DRM_FORMAT_RGB565;
>  	case PLANE_CTL_FORMAT_NV12:
>  		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_XYUV:
> +		return DRM_FORMAT_XYUV;
>  	default:
>  	case PLANE_CTL_FORMAT_XRGB_8888:
>  		if (rgb_order) {
> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>  		return PLANE_CTL_FORMAT_XRGB_2101010;
>  	case DRM_FORMAT_XBGR2101010:
>  		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> +	case DRM_FORMAT_XYUV:
> +		return PLANE_CTL_FORMAT_XYUV;
>  	case DRM_FORMAT_YUYV:
>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>  	case DRM_FORMAT_YVYU:
> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV:
>  		break;
>  	default:
>  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV:
>  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>  			return true;
>  		/* fall through */
> @@ -14517,6 +14525,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  		}
>  		break;
>  	case DRM_FORMAT_ABGR8888:
> +	case DRM_FORMAT_XYUV:
>  		if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&

VLV/CHV doesn't have this so this still looks like the wrong place.

>  		    INTEL_GEN(dev_priv) < 9) {
>  			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index c286dda625e4..2ac9471974c2 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1420,6 +1420,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV:
>  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>  			return true;
>  		/* fall through */
> -- 
> 2.17.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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