From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com, dri-devel@lists.freedesktop.org
Subject: [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV
Date: Fri, 7 Sep 2018 11:45:19 +0300 [thread overview]
Message-ID: <20180907084520.6349-2-stanislav.lisovskiy@intel.com> (raw)
In-Reply-To: <20180907084520.6349-1-stanislav.lisovskiy@intel.com>
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e2742c27..2ad09c7ecebc 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+ { .format = DRM_FORMAT_XYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9ae16a..5ba5b1473342 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -148,6 +148,7 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* 2 plane RGB + A
--
2.17.0
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next prev parent reply other threads:[~2018-09-07 8:45 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-07 8:45 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy
2018-09-07 8:45 ` Stanislav Lisovskiy [this message]
2018-09-07 8:45 ` [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
2018-09-07 9:00 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev6) Patchwork
2018-09-07 9:23 ` ✓ Fi.CI.BAT: success " Patchwork
2018-09-07 11:37 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-09-07 15:21 ` Martin Peres
2018-09-10 7:38 ` Lisovskiy, Stanislav
2018-09-12 13:29 ` ✓ Fi.CI.BAT: success " Patchwork
2018-09-12 18:55 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-14 13:36 ` [PATCH v10 0/2] Add XYUV format support Lisovskiy, Stanislav
2018-09-14 13:47 ` Ville Syrjälä
2018-09-14 14:30 ` Lisovskiy, Stanislav
2018-09-14 14:34 ` Saarinen, Jani
2018-09-14 14:49 ` [Intel-gfx] " Lisovskiy, Stanislav
2018-09-14 14:59 ` Alexandru-Cosmin Gheorghe
2018-09-17 8:27 ` [Intel-gfx] " Lisovskiy, Stanislav
2018-09-17 8:49 ` Alexandru-Cosmin Gheorghe
2018-09-14 17:05 ` Juha-Pekka Heikkilä
2018-09-17 8:25 ` [Intel-gfx] " Lisovskiy, Stanislav
2018-09-17 8:51 ` Juha-Pekka Heikkila
-- strict thread matches above, loose matches on Subject: below --
2018-10-02 11:15 Stanislav Lisovskiy
2018-10-02 11:15 ` [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
2018-10-02 15:28 ` Alexandru-Cosmin Gheorghe
2018-10-03 6:39 ` Lisovskiy, Stanislav
2018-10-03 8:07 ` Alexandru-Cosmin Gheorghe
2018-10-04 12:04 ` Lisovskiy, Stanislav
2018-10-04 12:25 ` Alexandru-Cosmin Gheorghe
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