From: Manasi Navare <manasi.d.navare@intel.com>
To: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
Date: Fri, 5 Oct 2018 12:03:48 -0700 [thread overview]
Message-ID: <20181005190348.GE4163@intel.com> (raw)
In-Reply-To: <20181005185643.31660-2-dhinakaran.pandiyan@intel.com>
On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote:
> The bits weren't defined in descending order.
> v2: Move definitions in a separate patch (Manasi)
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++----------
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 61148b9a4a8e..a98b95922818 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4584,6 +4584,15 @@ enum {
> #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> #define VIDEO_DIP_FREQ_MASK (3 << 16)
> /* HSW and later: */
> +#define DRM_DIP_ENABLE (1 << 28)
> +#define PSR_VSC_BIT_7_SET (1 << 27)
> +#define VSC_SELECT_MASK (0x3 << 25)
> +#define VSC_SELECT_SHIFT 25
> +#define VSC_DIP_HW_HEA_DATA (0 << 25)
> +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> +#define VSC_DIP_SW_HEA_DATA (3 << 25)
> +#define VDIP_ENABLE_PPS (1 << 24)
> #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
> #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
> #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
> @@ -4591,16 +4600,6 @@ enum {
> #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
>
> -#define DRM_DIP_ENABLE (1 << 28)
> -#define PSR_VSC_BIT_7_SET (1 << 27)
> -#define VSC_SELECT_MASK (0x3 << 25)
> -#define VSC_SELECT_SHIFT 25
> -#define VSC_DIP_HW_HEA_DATA (0 << 25)
> -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> -#define VSC_DIP_SW_HEA_DATA (3 << 25)
> -#define VDIP_ENABLE_PPS (1 << 24)
> -
> /* Panel power sequencing */
> #define PPS_BASE 0x61200
> #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
> --
> 2.17.1
>
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next prev parent reply other threads:[~2018-10-05 19:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-05 18:56 [PATCH 1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Dhinakaran Pandiyan
2018-10-05 18:56 ` [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place Dhinakaran Pandiyan
2018-10-05 19:03 ` Manasi Navare [this message]
2018-10-29 20:46 ` Dhinakaran Pandiyan
2018-10-05 19:44 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Patchwork
2018-10-06 2:00 ` ✓ Fi.CI.IGT: " Patchwork
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