From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Arthur J Runyan <arthur.j.runyan@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH] drm/i915/icl: MBUS B credit change
Date: Fri, 5 Oct 2018 14:01:03 -0700 [thread overview]
Message-ID: <20181005210103.GE16191@intel.com> (raw)
In-Reply-To: <5247b62d-6a05-6814-840a-266f927b98ca@intel.com>
On Fri, Oct 05, 2018 at 02:40:01PM +0530, Kumar, Mahesh wrote:
> Hi,
>
> LGTM
>
> Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
pushed to dinq adding also the rv-b from lucas
I got offline...
>
> On 10/4/2018 8:48 PM, Rodrigo Vivi wrote:
> > No functional change. But just a minor change to keep
> > up with Spec, since it has changed since commit c3cc39c539d4
> > ("drm/i915/icl: program mbus during pipe enable")
> >
> > The instructions previously said to program pipe's
> > B credit = 24 / number of pipes, which is 8 for ICL.
> > Now the spec gives us direct values independent of number
> > of pipes. Let's keep in sync.
> >
> > Also just a reorder on fields to make easier to compare
> > against spec's sequence: A -> BW -> B.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
> > Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 7 +++----
> > 1 file changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 36434c5359b1..eb2250a984a8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5683,10 +5683,9 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> > enum pipe pipe = crtc->pipe;
> > uint32_t val;
> > - val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
> > -
> > - /* Program B credit equally to all pipes */
> > - val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
> > + val = MBUS_DBOX_A_CREDIT(2);
> > + val |= MBUS_DBOX_BW_CREDIT(1);
> > + val |= MBUS_DBOX_B_CREDIT(8);
> > I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> > }
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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prev parent reply other threads:[~2018-10-05 21:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-04 15:18 [PATCH] drm/i915/icl: MBUS B credit change Rodrigo Vivi
2018-10-04 16:03 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-10-04 23:50 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-05 9:10 ` [PATCH] " Kumar, Mahesh
2018-10-05 21:01 ` Rodrigo Vivi [this message]
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