From: Patchwork <patchwork@emeril.freedesktop.org>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Limit number of scratch registers used for H2G
Date: Tue, 16 Oct 2018 10:08:23 -0000 [thread overview]
Message-ID: <20181016100823.2707.58080@emeril.freedesktop.org> (raw)
In-Reply-To: <20181016094207.22924-1-michal.wajdeczko@intel.com>
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Limit number of scratch registers used for H2G
URL : https://patchwork.freedesktop.org/series/51057/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7974be3e6bd9 drm/i915/guc: Limit number of scratch registers used for H2G
0f6ceeb6abe3 HAX enable GuC for CI
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
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next prev parent reply other threads:[~2018-10-16 10:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 9:42 [PATCH 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-16 9:42 ` [PATCH 2/2] HAX enable GuC for CI Michal Wajdeczko
2018-10-19 7:05 ` [LKP] 262bd453bf: drm:i915_gem_init_hw[i915]] kernel test robot
2018-10-16 10:08 ` Patchwork [this message]
2018-10-16 10:30 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Limit number of scratch registers used for H2G Patchwork
2018-10-16 11:44 ` [PATCH 1/2] " Chris Wilson
2018-10-16 16:26 ` Daniele Ceraolo Spurio
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