From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v4 2/2] HAX: Enable GuC for CI
Date: Fri, 19 Oct 2018 10:17:25 +0000 [thread overview]
Message-ID: <20181019101725.14024-2-michal.wajdeczko@intel.com> (raw)
In-Reply-To: <20181019101725.14024-1-michal.wajdeczko@intel.com>
GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
1.9.1
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next prev parent reply other threads:[~2018-10-19 10:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-19 10:17 [PATCH v4 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-19 10:17 ` Michal Wajdeczko [this message]
2018-11-05 0:23 ` [LKP] [HAX] ddc7f46e1c: drm:i915_gem_init_hw[i915]] kernel test robot
2018-10-22 11:20 ` ✗ Fi.CI.BAT: failure for series starting with [v4,1/2] drm/i915/guc: Limit number of scratch registers used for H2G Patchwork
2018-10-22 11:37 ` Chris Wilson
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