[PATCH] drm/i915: intel_pipe_config_compare: Don't compare DSI PLL regs when adjusting

From: Hans de Goede <j.w.r.degoede@gmail.com>
To: "Jani Nikula" <jani.nikula@linux.intel.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Daniel Vetter" <daniel@ffwll.ch>
Cc: Hans de Goede <hdegoede@redhat.com>,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel@lists.freedesktop.org
Subject: [PATCH] drm/i915: intel_pipe_config_compare: Don't compare DSI PLL regs when adjusting
Date: Fri,  2 Nov 2018 12:44:47 +0100	[thread overview]
Message-ID: <20181102114447.29501-1-hdegoede@redhat.com> (raw)

The GOP sometimes initializes the DSI pclk at a (slightly) different freq
then the pclk which we pick. intel_pipe_config_compare() allows for this
by doing a fuzzy compare on the port_clock.

But the pclk difference not only results in the port_clock and
base.adjusted_mode.crtc_clock clocks being a bit different, but also in
us picking different dsi_pll register values matching the different pclk.

This commit makes us only do the dsi_pll register compare when the adjust
parameter is false, so only from verify_crtc_state(), so that we correctly
do a fast modeset at boot avoiding the screen going black for about 1 sec.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b219d5858160..82fa85df0fba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11759,8 +11759,10 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 	PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
 	PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
 
-	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
-	PIPE_CONF_CHECK_X(dsi_pll.div);
+	if (!adjust) {
+		PIPE_CONF_CHECK_X(dsi_pll.ctrl);
+		PIPE_CONF_CHECK_X(dsi_pll.div);
+	}
 
 	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
 		PIPE_CONF_CHECK_I(pipe_bpp);
-- 
2.19.0

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