From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH v4 2/4] drm/i915/psr: Always wait for idle state when disabling PSR
Date: Tue, 6 Nov 2018 11:08:41 -0800 [thread overview]
Message-ID: <20181106190843.18009-2-jose.souza@intel.com> (raw)
In-Reply-To: <20181106190843.18009-1-jose.souza@intel.com>
It should always wait for idle state when disabling PSR because PSR
could be inactive due a call to intel_psr_exit() and while PSR is
still being disabled asynchronously userspace could change the
modeset causing a call to psr_disable() that will not wait for PSR
idle and then PSR will be enabled again while PSR is still not idle.
v2: rebased on top of the patch reusing psr_exit()
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 41 ++++++++++++++------------------
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2ecc2db67395..81ec31784766 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -661,8 +661,12 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
{
u32 val;
- if (!dev_priv->psr.active)
+ if (!dev_priv->psr.active) {
+ if (INTEL_GEN(dev_priv) >= 9)
+ WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
+ WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
return;
+ }
if (dev_priv->psr.psr2_enabled) {
val = I915_READ(EDP_PSR2_CTL);
@@ -680,32 +684,23 @@ static void
intel_psr_disable_source(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ i915_reg_t psr_status;
+ u32 psr_status_mask;
- if (dev_priv->psr.active) {
- i915_reg_t psr_status;
- u32 psr_status_mask;
-
- intel_psr_exit(dev_priv);
+ intel_psr_exit(dev_priv);
- if (dev_priv->psr.psr2_enabled) {
- psr_status = EDP_PSR2_STATUS;
- psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
- } else {
- psr_status = EDP_PSR_STATUS;
- psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
- }
-
- /* Wait till PSR is idle */
- if (intel_wait_for_register(dev_priv,
- psr_status, psr_status_mask, 0,
- 2000))
- DRM_ERROR("Timed out waiting for PSR Idle State\n");
+ if (dev_priv->psr.psr2_enabled) {
+ psr_status = EDP_PSR2_STATUS;
+ psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
- if (dev_priv->psr.psr2_enabled)
- WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
- else
- WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+ psr_status = EDP_PSR_STATUS;
+ psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
}
+
+ /* Wait till PSR is idle */
+ if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
+ 2000))
+ DRM_ERROR("Timed out waiting PSR idle state\n");
}
static void intel_psr_disable_locked(struct intel_dp *intel_dp)
--
2.19.1
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next prev parent reply other threads:[~2018-11-06 19:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-06 19:08 [PATCH v4 1/4] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() José Roberto de Souza
2018-11-06 19:08 ` José Roberto de Souza [this message]
2018-11-06 19:08 ` [PATCH v4 3/4] drm/i915/icl: Reset PSR interruptions José Roberto de Souza
2018-11-06 19:08 ` [PATCH v4 4/4] drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked() José Roberto de Souza
2018-11-07 13:00 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/4] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() Patchwork
2018-11-08 1:13 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-11-08 2:13 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-08 21:02 ` Patchwork
2018-11-09 6:36 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-09 18:53 ` Souza, Jose
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