Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> Having completed a test run of gem_eio across all machines in CI we also
> observe the phenomenon (of lost interrupts after resetting the GPU) on
> gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> the same HWSTAM workaround that was effective for gen6+ for all, as
> although we haven't seen the same failure on gen4/5 it seems prudent to
> keep the code the same.
> 
> As a consequence we can remove the extra setting of HWSTAM and apply the
> register from a single site.
> 
> v2: Delazy and move the HWSTAM into its own function
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
>  2 files changed, 27 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2dac9b5f4ce..0c7fc9890891 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (IS_GEN(dev_priv, 5))
> -		I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET(DE);
>  	if (IS_GEN(dev_priv, 7))
>  		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE16(HWSTAM, 0xffff);
> -
>  	GEN2_IRQ_RESET();
>  }
>  
> @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }
>  
> @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }

So we're not worried about enabling interrupts and having
something unmasked in HWSTAM by accident before we have the
status page set up?

>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdeca2b877c9..10e7b7a6ba88 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -393,12 +393,38 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
>  	I915_WRITE(HWS_PGA, addr);
>  }
>  
> +static void set_hwstam_mask(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
> +	u32 mask = ~0u;
> +
> +	/*
> +	 * Keep the render interrupt unmasked as this papers over
> +	 * lost interrupts following a reset.
> +	 */
> +	if (engine->id == RCS) {
> +		if (INTEL_GEN(dev_priv) >= 6)
> +			mask &= ~BIT(0);
> +		else
> +			mask &= ~I915_USER_INTERRUPT;
> +	}
> +
> +	if (INTEL_GEN(dev_priv) >= 3)
> +		I915_WRITE(hwstam, mask);
> +	else
> +		I915_WRITE16(hwstam, mask);
> +}
> +
>  static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	i915_reg_t mmio;
>  
> -	/* The ring status page addresses are no longer next to the rest of
> +	set_hwstam_mask(engine);
> +
> +	/*
> +	 * The ring status page addresses are no longer next to the rest of
>  	 * the ring registers as of gen7.
>  	 */
>  	if (IS_GEN(dev_priv, 7)) {
> @@ -428,19 +454,6 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  		mmio = RING_HWS_PGA(engine->mmio_base);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> -		u32 mask = ~0u;
> -
> -		/*
> -		 * Keep the render interrupt unmasked as this papers over
> -		 * lost interrupts following a reset.
> -		 */
> -		if (engine->id == RCS)
> -			mask &= ~BIT(0);
> -
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
> -	}
> -
>  	I915_WRITE(mmio, engine->status_page.ggtt_offset);
>  	POSTING_READ(mmio);
>  
> -- 
> 2.20.0
> 
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-- 
Ville Syrjälä
Intel
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