From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 06/13] drm/i915: Move LUT programming to happen after vblank waits
Date: Thu, 7 Feb 2019 21:24:24 +0200 [thread overview]
Message-ID: <20190207192424.GN20097@intel.com> (raw)
In-Reply-To: <bd64454b-25ae-1ab0-347b-b5cd4d7a68cf@linux.intel.com>
On Thu, Feb 07, 2019 at 04:46:54PM +0100, Maarten Lankhorst wrote:
> Hey,
>
> Op 05-02-2019 om 17:08 schreef Ville Syrjala:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The LUTs are single buffered so we should program them after
> > the double buffered pipe updates have been latched by the
> > hardware.
> >
> > We'll also fix up the IPS vs. split gamma w/a to do the IPS
> > disable like everyone else. Note that this is currently dead
> > code as we don't use the split gamma mode on HSW, but that
> > will be fixed up shortly.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Hmm I guess there is no good way to do this, either before or after. :/
>
> The idea was that we do it before was to make sure that the frame after the flip would be perfect. I guess
>
> we can't be sure, and after is as good as before..
After is much better than before since we have actually have a
chance that we're inside the correct vblank interval. Doing it before
guarantees that we're either in the middle of the previous frame or in
the vblank before the previous frame (which would make the entire
previous frame use the wrong LUT values).
Anyways, it should be mostly OK for single pipe updates since
we'll just wait for the vblank of that one pipe, and thus should still
be in the vblank for the LUT reprogramming. For multi-pipe we'd need to
get significantly more lucky.
>
> For patch 1-6:
>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2019-02-07 19:24 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-05 16:08 [PATCH v2 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 01/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 02/13] drm/i915: Precompute gamma_mode Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 03/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 04/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 05/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 06/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
2019-02-07 15:46 ` Maarten Lankhorst
2019-02-07 19:24 ` Ville Syrjälä [this message]
2019-02-05 16:08 ` [PATCH v2 07/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
2019-02-07 15:49 ` Maarten Lankhorst
2019-02-07 16:27 ` Ville Syrjälä
2019-02-07 17:27 ` Ville Syrjälä
2019-02-08 8:51 ` Maarten Lankhorst
2019-02-05 16:08 ` [PATCH v2 08/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 09/13] drm/i915: Track pipe csc enable " Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 10/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 11/13] drm/i915: Turn off pipe CSC " Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 12/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 13/13] drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable() Ville Syrjala
2019-02-07 15:58 ` Maarten Lankhorst
2019-02-07 16:29 ` Ville Syrjälä
2019-02-05 16:57 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8 (rev2) Patchwork
2019-02-05 17:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-02-05 17:24 ` ✓ Fi.CI.BAT: success " Patchwork
2019-02-05 21:19 ` ✓ Fi.CI.IGT: " Patchwork
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