From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 7/9] drm/i915: Move some variables to tighter scope
Date: Wed, 20 Mar 2019 17:27:36 +0200 [thread overview]
Message-ID: <20190320152736.GO3888@intel.com> (raw)
In-Reply-To: <20190319001049.GQ4773@mdroper-desk.amr.corp.intel.com>
On Mon, Mar 18, 2019 at 05:10:49PM -0700, Matt Roper wrote:
> On Tue, Mar 12, 2019 at 10:58:42PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Clean up skl_allocate_pipe_ddb() a bit by moving the 'wm' variable
> > to tighter scope. We'll also consitify it where appropriate.
> >
> > Cc: Neel Desai <neel.desai@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++----------
> > 1 file changed, 13 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 8afbc56ad89a..b958a1a00014 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4336,7 +4336,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
> > - struct skl_plane_wm *wm;
> > u16 alloc_size, start = 0;
> > u16 total[I915_MAX_PLANES] = {};
> > u16 uv_total[I915_MAX_PLANES] = {};
> > @@ -4393,7 +4392,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> > blocks = 0;
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > + const struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> >
> > if (plane_id == PLANE_CURSOR) {
> > if (WARN_ON(wm->wm[level].min_ddb_alloc >
> > @@ -4427,6 +4427,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > * proportional to its relative data rate.
> > */
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > + const struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> > u64 rate;
> > u16 extra;
> >
> > @@ -4440,8 +4442,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > if (total_data_rate == 0)
> > break;
> >
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > -
> > rate = plane_data_rate[plane_id];
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate,
> > @@ -4466,14 +4466,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > /* Set the actual DDB start/end points for each plane */
> > start = alloc->start;
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - struct skl_ddb_entry *plane_alloc, *uv_plane_alloc;
> > + struct skl_ddb_entry *plane_alloc =
> > + &cstate->wm.skl.plane_ddb_y[plane_id];
> > + struct skl_ddb_entry *uv_plane_alloc =
> > + &cstate->wm.skl.plane_ddb_uv[plane_id];
> >
> > if (plane_id == PLANE_CURSOR)
> > continue;
> >
> > - plane_alloc = &cstate->wm.skl.plane_ddb_y[plane_id];
> > - uv_plane_alloc = &cstate->wm.skl.plane_ddb_uv[plane_id];
> > -
> > /* Gen11+ uses a separate plane for UV watermarks */
> > WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> >
>
> This hunk is fine, but isn't what's described in the commit message.
> Maybe throw an extra sentence in there referencing this change?
Amended the commit message a bit, and fixed up the update vs. build
typo in the commit message of the other patch.
Series pushed to dinq. Thanks for the review.
>
> Aside from that,
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> > @@ -4499,7 +4499,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > */
> > for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > + struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> >
> > /*
> > * We only disable the watermarks for each plane if
> > @@ -4535,7 +4536,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > * don't have enough DDB blocks for it.
> > */
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > + struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> > +
> > if (wm->trans_wm.plane_res_b >= total[plane_id])
> > memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
> > }
> > --
> > 2.19.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-03-20 15:27 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-12 20:58 [PATCH 0/9] skl+ cursor DDB allocation fixes Ville Syrjala
2019-03-12 20:58 ` [PATCH 1/9] drm/i915: Accept alloc_size == blocks Ville Syrjala
2019-03-12 20:58 ` [PATCH 2/9] drm/i915: Don't pass plane state to skl_compute_plane_wm() Ville Syrjala
2019-03-12 20:58 ` [PATCH 3/9] drm/i915: Extract skl_compute_wm_params() Ville Syrjala
2019-03-12 20:58 ` [PATCH 4/9] drm/i915: Allocate enough DDB for the cursor Ville Syrjala
2019-03-19 10:51 ` Ville Syrjälä
2019-03-19 16:03 ` [PATCH v2 " Ville Syrjala
2019-03-12 20:58 ` [PATCH 5/9] drm/i915: Make sure cursor has enough ddb for the selected wm level Ville Syrjala
2019-03-12 20:58 ` [PATCH 6/9] drm/i915: Keep plane watermarks enabled more aggressively Ville Syrjala
2019-03-19 0:09 ` Matt Roper
2019-03-12 20:58 ` [PATCH 7/9] drm/i915: Move some variables to tighter scope Ville Syrjala
2019-03-19 0:10 ` Matt Roper
2019-03-20 15:27 ` Ville Syrjälä [this message]
2019-03-12 20:58 ` [PATCH 8/9] drm/i915: Don't pass pipe_wm around so much Ville Syrjala
2019-03-19 0:10 ` Matt Roper
2019-03-12 20:58 ` [PATCH 9/9] drm/i915: Inline skl_build_pipe_wm() into its only caller Ville Syrjala
2019-03-19 0:11 ` Matt Roper
2019-03-19 10:49 ` Ville Syrjälä
2019-03-13 15:34 ` ✗ Fi.CI.SPARSE: warning for skl+ cursor DDB allocation fixes Patchwork
2019-03-13 16:15 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-13 20:41 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-03-14 17:11 ` Ville Syrjälä
2019-03-19 16:41 ` ✗ Fi.CI.SPARSE: warning for skl+ cursor DDB allocation fixes (rev2) Patchwork
2019-03-19 17:14 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-20 2:41 ` ✓ Fi.CI.IGT: " Patchwork
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