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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [PATCH v3 1/5] drm/i915/bdw+: Move misc display IRQ handling to it own function
Date: Mon, 15 Apr 2019 14:54:51 -0700	[thread overview]
Message-ID: <20190415215455.9176-1-jose.souza@intel.com> (raw)

Just moving it to reduce the tabs and avoid break code lines.
No behavior changes intended here.

v2:
- Reading misc display IRQ outside of gen8_de_misc_irq_handler() as
other irq handlers (Dhinakaran)

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 45 ++++++++++++++++++---------------
 1 file changed, 25 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d934545445e1..820d89300454 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2740,6 +2740,28 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 	return mask;
 }
 
+static void
+gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
+{
+	bool found = false;
+
+	if (iir & GEN8_DE_MISC_GSE) {
+		intel_opregion_asle_intr(dev_priv);
+		found = true;
+	}
+
+	if (iir & GEN8_DE_EDP_PSR) {
+		u32 psr_iir = I915_READ(EDP_PSR_IIR);
+
+		intel_psr_irq_handler(dev_priv, psr_iir);
+		I915_WRITE(EDP_PSR_IIR, psr_iir);
+		found = true;
+	}
+
+	if (!found)
+		DRM_ERROR("Unexpected DE Misc interrupt\n");
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2750,29 +2772,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	if (master_ctl & GEN8_DE_MISC_IRQ) {
 		iir = I915_READ(GEN8_DE_MISC_IIR);
 		if (iir) {
-			bool found = false;
-
 			I915_WRITE(GEN8_DE_MISC_IIR, iir);
 			ret = IRQ_HANDLED;
-
-			if (iir & GEN8_DE_MISC_GSE) {
-				intel_opregion_asle_intr(dev_priv);
-				found = true;
-			}
-
-			if (iir & GEN8_DE_EDP_PSR) {
-				u32 psr_iir = I915_READ(EDP_PSR_IIR);
-
-				intel_psr_irq_handler(dev_priv, psr_iir);
-				I915_WRITE(EDP_PSR_IIR, psr_iir);
-				found = true;
-			}
-
-			if (!found)
-				DRM_ERROR("Unexpected DE Misc interrupt\n");
-		}
-		else
+			gen8_de_misc_irq_handler(dev_priv, iir);
+		} else {
 			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
+		}
 	}
 
 	if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
-- 
2.21.0

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             reply	other threads:[~2019-04-15 21:54 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-15 21:54 José Roberto de Souza [this message]
2019-04-15 21:54 ` [PATCH v3 2/5] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
2019-04-15 21:54 ` [PATCH v3 3/5] drm/i915: Add _TRANS2() José Roberto de Souza
2019-04-15 21:54 ` [PATCH v3 4/5] drm/i915: Make PSR registers relative to transcoders José Roberto de Souza
2019-04-16  9:07   ` Jani Nikula
2019-04-15 21:54 ` [PATCH v3 5/5] drm/i915: Add transcoder parameter to PSR registers macros José Roberto de Souza
2019-04-15 22:13 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915/bdw+: Move misc display IRQ handling to it own function Patchwork
2019-04-15 22:15 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-04-15 22:42 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-16  0:24 ` ✓ Fi.CI.IGT: " Patchwork

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