From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/i915: skip the second CRC even for GEN 7 GPUs
Date: Thu, 16 May 2019 16:30:31 +0300 [thread overview]
Message-ID: <20190516133031.GN24299@intel.com> (raw)
In-Reply-To: <87a7fma79e.fsf@intel.com>
On Thu, May 16, 2019 at 03:55:25PM +0300, Jani Nikula wrote:
> On Thu, 16 May 2019, Maarten Lankhorst <maarten.lankhorst@linux.intel.com> wrote:
> > Op 16-05-2019 om 07:58 schreef Harish Chegondi:
> >> display_pipe_crc_irq_handler() skips the first CRC for all GPUs and the
> >> second CRC for GEN8+ GPUs. The second CRC is invalid even for BYT which
> >> is a GEN7 GPU. So, skip the second CRC even for GEN7 GPUs.
> >>
> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
> >> Cc: Petri Latvala <petri.latvala@intel.com>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> >> References: https://bugs.freedesktop.org/show_bug.cgi?id=103191
> >> ---
> >> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> >> index 233211fde0ea..3809e9f7fae2 100644
> >> --- a/drivers/gpu/drm/i915/i915_irq.c
> >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> >> @@ -1775,11 +1775,11 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> >> * bonkers. So let's just wait for the next vblank and read
> >> * out the buggy result.
> >> *
> >> - * On GEN8+ sometimes the second CRC is bonkers as well, so
> >> + * On GEN7+ sometimes the second CRC is bonkers as well, so
> >> * don't trust that one either.
> >> */
> >> if (pipe_crc->skipped <= 0 ||
> >> - (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
> >> + (INTEL_GEN(dev_priv) >= 7 && pipe_crc->skipped == 1)) {
> >> pipe_crc->skipped++;
> >> spin_unlock(&pipe_crc->lock);
> >> return;
> >
> > I would be interested in the results, haswell is different from
> > VLV. Has it ever been observed on that platform?
>
> Good point. I looked at [1] which I presumed was on VLV, but it says
> nothing about HSW.
This whole thing is just a pile of duct tape anyway. The reason(s)
for these funky crcs has never been properly analysed.
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2019-05-16 13:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-16 5:58 [PATCH 0/1] Reg: igt@kms_pipe_crc_basic@* CRC mismatch test failures Harish Chegondi
2019-05-16 5:58 ` [PATCH 1/1] drm/i915: skip the second CRC even for GEN 7 GPUs Harish Chegondi
2019-05-16 8:30 ` Jani Nikula
2019-05-16 12:46 ` Maarten Lankhorst
2019-05-16 12:55 ` Jani Nikula
2019-05-16 13:30 ` Ville Syrjälä [this message]
2019-05-16 15:46 ` Jani Nikula
2019-05-16 21:02 ` Chegondi, Harish
2019-05-16 20:52 ` Chegondi, Harish
2019-10-23 7:24 ` [PATCH v2 0/1] Invalid CRCs causing CRC mismatch test failures Harish Chegondi
2019-10-23 7:24 ` [PATCH v2 1/1] drm/i915: skip the second CRC even for GEN 7 GPUs Harish Chegondi
2019-10-23 22:15 ` Chegondi, Harish
2019-10-23 22:15 ` [Intel-gfx] " Chegondi, Harish
2019-10-23 8:08 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/1] " Patchwork
2019-05-16 6:33 ` ✓ Fi.CI.BAT: success for Reg: igt@kms_pipe_crc_basic@* CRC mismatch test failures Patchwork
2019-05-16 7:51 ` ✓ Fi.CI.IGT: " Patchwork
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