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From: Patchwork <patchwork@emeril.freedesktop.org>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture
Date: Fri, 07 Jun 2019 09:32:29 -0000	[thread overview]
Message-ID: <20190607093229.32139.6182@emeril.freedesktop.org> (raw)
In-Reply-To: <20190607082557.31670-1-tvrtko.ursulin@linux.intel.com>

== Series Details ==

Series: series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture
URL   : https://patchwork.freedesktop.org/series/61758/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9a057903722f drm/i915: Reset only affected engines when handling error capture
2467bef6dc38 drm/i915: Tidy engine mask types in hangcheck
e71b4d115e62 drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:71:
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:74:
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~clear__; \
+	__val |= set__; \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})

-:27: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'clear__' may be better as '(clear__)' to avoid precedence issues
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~clear__; \
+	__val |= set__; \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})

total: 0 errors, 0 warnings, 4 checks, 52 lines checked
bcda7ed91c02 drm/i915: Extract engine fault reset to a helper
1390b7f7f35b drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt

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  parent reply	other threads:[~2019-06-07  9:32 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-07  8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
2019-06-07  8:25 ` [CI 2/5] drm/i915: Tidy engine mask types in hangcheck Tvrtko Ursulin
2019-06-07  8:25 ` [CI 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric Tvrtko Ursulin
2019-06-07  9:09   ` [CI v2 3/8] " Tvrtko Ursulin
2019-06-07 10:15   ` [CI v3 3/5] " Tvrtko Ursulin
2019-06-07  8:25 ` [CI 4/5] drm/i915: Extract engine fault reset to a helper Tvrtko Ursulin
2019-06-07  8:25 ` [CI 5/5] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt Tvrtko Ursulin
2019-06-07  9:32 ` Patchwork [this message]
2019-06-07 10:20 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture Patchwork
2019-06-07 10:41 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3) Patchwork
2019-06-07 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-09 18:41 ` ✗ Fi.CI.IGT: failure " Patchwork

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