Re: [PATCH 1/3] drm/i915/icl: Add new supported CD clocks

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915/icl: Add new supported CD clocks
Date: Wed, 19 Jun 2019 14:48:48 +0300	[thread overview]
Message-ID: <20190619114848.GX5942@intel.com> (raw)
In-Reply-To: <20190618225035.31816-1-jose.souza@intel.com>

On Tue, Jun 18, 2019 at 03:50:33PM -0700, José Roberto de Souza wrote:
> Now 180, 172.8 and 192 MHz are supported.
> 
> 180 and 172.8 MHz CD clocks will only be used when audio is not
> enabled as state by BSpec and implemented in
> intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
> Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48 MHz
> but we are not reading it.
> 
> BSpec: 20598
> BSpec: 15729
> Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 29 +++++++++++++++-------
>  1 file changed, 20 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8993ab283562..d560e25d3fb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1756,9 +1756,10 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  
>  static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
>  {
> -	int ranges_24[] = { 312000, 552000, 648000 };
> -	int ranges_19_38[] = { 307200, 556800, 652800 };
> -	int *ranges;
> +	const int ranges_24[] = { 180000, 192000, 312000, 552000, 648000 };
> +	const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };

static?

> +	const int *ranges;
> +	unsigned int len, i;

just 'int' please

>  
>  	switch (ref) {
>  	default:
> @@ -1766,19 +1767,22 @@ static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
>  		/* fall through */
>  	case 24000:
>  		ranges = ranges_24;
> +		len = ARRAY_SIZE(ranges_24);
>  		break;
>  	case 19200:
>  	case 38400:
>  		ranges = ranges_19_38;
> +		len = ARRAY_SIZE(ranges_19_38);
>  		break;
>  	}
>  
> -	if (min_cdclk > ranges[1])
> -		return ranges[2];
> -	else if (min_cdclk > ranges[0])
> -		return ranges[1];
> -	else
> -		return ranges[0];
> +	for (i = 0; i < len; i++) {
> +		if (min_cdclk <= ranges[i])
> +			return ranges[i];
> +	}
> +
> +	WARN_ON(min_cdclk > ranges[len - 1]);
> +	return ranges[len - 1];
>  }
>  
>  static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> @@ -1792,16 +1796,23 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  	default:
>  		MISSING_CASE(cdclk);
>  		/* fall through */
> +	case 172800:
>  	case 307200:
>  	case 556800:
>  	case 652800:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
>  			dev_priv->cdclk.hw.ref != 38400);
>  		break;
> +	case 180000:
>  	case 312000:
>  	case 552000:
>  	case 648000:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> +		break;
> +	case 192000:
> +		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> +			dev_priv->cdclk.hw.ref != 38400 &&
> +			dev_priv->cdclk.hw.ref != 24000);

I'd probably put a break here too for symmetry.

>  	}
>  
>  	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> -- 
> 2.22.0
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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