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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
Date: Wed, 10 Jul 2019 22:15:05 +0300	[thread overview]
Message-ID: <20190710191505.GM5942@intel.com> (raw)
In-Reply-To: <20190710000613.18866-1-manasi.d.navare@intel.com>

On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> On TGL+ we support 8K display resolution, hence bump up the vertical
> active limits to 4320 in intel_mode_valid()
> 
> v2:
> * Checkpatch warning (Manasi)
> 
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f07081815b80..cfceb27e4b9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
>  			   DRM_MODE_FLAG_CLKDIV2))
>  		return MODE_BAD;
>  
> -	if (INTEL_GEN(dev_priv) >= 9 ||
> -	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		hdisplay_max = 8192;
> +		vdisplay_max = 4320;
> +		htotal_max = 8192;
> +		vtotal_max = 8192;

I wonder if we can safely bump these before we get the joiner stuff sorted.
Hmm. I guess it should be fine as the limit that is supposed to overcome
is caused by the cdclk max frequency being too low to allow a single
pipe to push enough pixels. And since we check that in .mode_valid() we
shouldn't accidentally start to advertize support for modes we can't do.

Which means these limits should actually be higher than this. 16k for
htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe.

> +	} else if (INTEL_GEN(dev_priv) >= 9 ||
> +		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
>  		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
>  		vdisplay_max = 4096;
>  		htotal_max = 8192;
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2019-07-10 19:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare
2019-07-09 21:47 ` [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height " Manasi Navare
2019-07-09 23:07   ` Souza, Jose
2019-07-10 18:57     ` Manasi Navare
2019-07-10 19:18   ` Ville Syrjälä
2019-07-10 19:36     ` Manasi Navare
2019-07-09 22:07 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits " Patchwork
2019-07-09 22:49 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-09 23:04 ` [PATCH 1/2] " Souza, Jose
2019-07-10 18:57   ` Manasi Navare
2019-07-10  0:06 ` [PATCH v2] " Manasi Navare
2019-07-10 19:15   ` Ville Syrjälä [this message]
2019-07-10 19:24     ` Manasi Navare
2019-07-10 19:30       ` Ville Syrjälä
2019-07-10  0:40 ` ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) Patchwork
2019-07-11  9:07 ` ✓ Fi.CI.IGT: " Patchwork

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