From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453
Date: Mon, 12 Aug 2019 15:10:33 -0700 [thread overview]
Message-ID: <20190812221033.GA16513@InViCtUs> (raw)
In-Reply-To: <20190726000226.26914-4-lucas.demarchi@intel.com>
On Thu, Jul 25, 2019 at 05:02:26PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Enable Small PL for power benefit.
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demarchi@intel.com
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3235ef355dfd..830ccd416a29 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1279,6 +1279,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> wa_write_or(wal,
> GEN12_L3SQCREG2,
> GEN12_LQSC_FLUSH_COHERENT_LINES);
> +
> + /* Wa_1406941453:tgl */
> + wa_masked_en(wal,
> + SAMPLER_MODE,
> + SAMPLER_ENABLE_SMALL_PL);
> }
>
> if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fbbb89f6ca2f..71efb37f54a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8965,6 +8965,9 @@ enum {
> #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
> #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
>
> +#define SAMPLER_MODE _MMIO(0xe18c)
> +#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
> +
> #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
> #define FLOW_CONTROL_ENABLE (1 << 15)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-08-12 22:09 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-26 0:02 [PATCH 0/3] Tiger Lake: add workarounds Lucas De Marchi
2019-07-26 0:02 ` [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds Lucas De Marchi
2019-08-12 22:29 ` Radhakrishna Sripada
2019-08-13 18:07 ` Radhakrishna Sripada
2019-08-16 2:47 ` Lucas De Marchi
2019-07-26 0:02 ` [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607 Lucas De Marchi
2019-07-26 0:10 ` Chris Wilson
2019-07-26 13:15 ` Tvrtko Ursulin
2019-07-26 13:20 ` Chris Wilson
2019-07-26 13:34 ` Tvrtko Ursulin
2019-07-26 13:55 ` Chris Wilson
2019-07-26 0:02 ` [PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
2019-08-12 22:10 ` Radhakrishna Sripada [this message]
2019-07-26 2:47 ` ✓ Fi.CI.BAT: success for Tiger Lake: add workarounds Patchwork
2019-07-27 4:36 ` ✓ Fi.CI.IGT: " Patchwork
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