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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/3] drm/i915/icl: Add command cache invalidate
Date: Thu, 15 Aug 2019 11:30:54 +0300	[thread overview]
Message-ID: <20190815083055.14132-2-mika.kuoppala@linux.intel.com> (raw)
In-Reply-To: <20190815083055.14132-1-mika.kuoppala@linux.intel.com>

On the set of invalidations, we need to add command
cache invalidate as a new domain.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 929a17e54f2c..86e00a2db8a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -208,6 +208,7 @@
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
 #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6a27a897d7a6..9018afb4e9ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2691,6 +2691,7 @@ static int gen11_emit_flush_render(struct i915_request *request,
 
 		flags |= PIPE_CONTROL_CS_STALL;
 
+		flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
-- 
2.17.1

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  reply	other threads:[~2019-08-15  8:31 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-15  8:30 [PATCH 1/3] drm/i915/icl: Implement gen11 flush including tile cache Mika Kuoppala
2019-08-15  8:30 ` Mika Kuoppala [this message]
2019-08-15  8:30 ` [PATCH 3/3] drm/i915/icl: Add gen11 specific render breadcrumbs Mika Kuoppala
2019-08-15  9:08   ` Chris Wilson
2019-08-15  9:49     ` Mika Kuoppala
2019-08-15  8:44 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/icl: Implement gen11 flush including tile cache Patchwork
2019-08-15  9:09 ` [PATCH 1/3] " Chris Wilson
2019-08-15  9:10 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2019-08-15 11:40 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/icl: Implement gen11 flush including tile cache (rev2) Patchwork
2019-08-15 12:01 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-15 22:37 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/icl: Implement gen11 flush including tile cache Patchwork
2019-08-16  4:10 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/icl: Implement gen11 flush including tile cache (rev2) Patchwork

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