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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH v8 2/3] drm/i915: Add transcoder restriction to PSR2
Date: Wed, 21 Aug 2019 09:33:56 +0530	[thread overview]
Message-ID: <20190821040355.GA30506@intel.com> (raw)
In-Reply-To: <20190820223325.27490-2-jose.souza@intel.com>

On 2019-08-20 at 15:33:24 -0700, José Roberto de Souza wrote:
> According to PSR2_CTL definition in BSpec there is only one instance
> of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2
> on TRANSCODER_EDP while on TGL PSR2 is only supported by
> TRANSCODER_A.
> 
> Since BDW PSR is allowed on any port, but we need to restrict by
> transcoder.
> 
> v8: Renamed _psr2_supported_in_trans() to psr2_supported() (Lucas)
> 
> BSpec: 7713
> BSpec: 20584
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 77232f6bca17..1dafe326edda 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -534,6 +534,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
>  }
>  
> +static bool
> +psr2_supported(struct drm_i915_private *dev_priv, enum transcoder trans)
> +{
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return trans == TRANSCODER_A;
> +	else
> +		return trans == TRANSCODER_EDP;
> +}
> +
>  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  				    struct intel_crtc_state *crtc_state)
>  {
> @@ -545,6 +554,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	if (!dev_priv->psr.sink_psr2_support)
>  		return false;
>  
> +	if (!psr2_supported(dev_priv, crtc_state->cpu_transcoder)) {
> +		DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",
> +			      transcoder_name(crtc_state->cpu_transcoder));
> +		return false;
> +	}
> +
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>  	/*
>  	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
>  	 * resolution requires DSC to be enabled, priority is given to DSC
> -- 
> 2.22.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2019-08-21  4:07 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-20 22:33 [PATCH v8 1/3] drm/i915/psr: Make PSR registers relative to transcoders José Roberto de Souza
2019-08-20 22:33 ` [PATCH v8 2/3] drm/i915: Add transcoder restriction to PSR2 José Roberto de Souza
2019-08-21  4:03   ` Anshuman Gupta [this message]
2019-08-20 22:33 ` [PATCH v8 3/3] drm/i915: Do not unmask PSR interruption in IRQ postinstall José Roberto de Souza
2019-08-20 22:57   ` Lucas De Marchi
2019-08-20 23:09 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative to transcoders Patchwork
2019-08-20 23:32 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-21  4:36 ` [PATCH v8 1/3] " Anshuman Gupta
2019-08-21 20:06   ` Souza, Jose
2019-08-22 16:07     ` Gupta, Anshuman
2019-08-22 16:49       ` Souza, Jose
2019-08-22 17:09         ` Gupta, Anshuman
2019-08-22 17:22           ` Souza, Jose
2019-08-21 13:13 ` ✓ Fi.CI.IGT: success for series starting with [v8,1/3] " Patchwork
2019-08-22 20:24   ` Souza, Jose

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