From: Imre Deak <imre.deak@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 7/9] drm/i915/tgl: Fix dkl link training
Date: Tue, 24 Sep 2019 18:58:37 +0300 [thread overview]
Message-ID: <20190924155837.GC25906@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20190923195513.207536-8-jose.souza@intel.com>
On Mon, Sep 23, 2019 at 12:55:11PM -0700, José Roberto de Souza wrote:
> Link training is failling when running link at 2.7GHz and 1.62GHz and
> following BSpec pll algorithm.
>
> Comparing the values calculated and the ones from the reference table
> it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
> to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on
> div2 value, that matches with dkl hardcoded table.
>
> So implementing this way as it proved to work in HW and leaving a
> comment so we know why it do not match BSpec.
>
> Issue reported on BSpec 49204.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 496df4095a21..3c881d4cf973 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2631,7 +2631,12 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>
> if (div2 >= 2) {
> if (is_dkl) {
> - a_divratio = 5;
> + /*
> + * Note: a_divratio not matching TGL
> + * BSpec algorithm but matching
> + * hardcoded values and working on HW
> + */
> + a_divratio = 10;
Yes, matches the hardcoded values for CLKTOP2_HSCLKCTL/CORECLKCTL1, with
the exception that the hardcoded value for CLKTOP2_HSCLKCTL 5p4 is also
incorrect wrt. div2 within that (should be 1 but it's 2).
However we don't have any hardcoded values in Bspec for HDMI except for
the 5.94Gbps/div2=1 case. So until otherwise proven, for HDMI/div2>=2 I
wouldn't change the value, rather have the same logic as for ICL that is
is_dp ? 10 : 5;
> tlinedrv = 1;
> } else {
> a_divratio = is_dp ? 10 : 5;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-09-24 15:59 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 19:55 [PATCH v3 0/9] TGL TC enabling v3 José Roberto de Souza
2019-09-23 19:55 ` [PATCH v3 1/9] drm/i915/tgl: Add initial dkl pll support José Roberto de Souza
2019-09-24 14:20 ` Imre Deak
2019-09-24 20:20 ` Souza, Jose
2019-09-23 19:55 ` [PATCH v3 2/9] drm/i915/tgl: Add support for dkl pll write José Roberto de Souza
2019-09-23 19:55 ` [PATCH v3 3/9] drm/i915/tgl: TC helper function to return pin mapping José Roberto de Souza
2019-09-23 19:55 ` [PATCH v3 4/9] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
2019-09-23 22:02 ` Lucas De Marchi
2019-09-24 13:00 ` Imre Deak
2019-09-24 23:21 ` Souza, Jose
2019-09-25 14:26 ` Imre Deak
2019-09-25 16:12 ` Lucas De Marchi
2019-09-23 19:55 ` [PATCH v3 5/9] drm/i915/tgl: re-indent code to prepare for DKL changes José Roberto de Souza
2019-09-23 22:04 ` Lucas De Marchi
2019-09-24 20:58 ` Matt Roper
2019-09-23 19:55 ` [PATCH v3 6/9] drm/i915/tgl: Add dkl phy pll calculations José Roberto de Souza
2019-09-23 22:04 ` Lucas De Marchi
2019-09-23 19:55 ` [PATCH v3 7/9] drm/i915/tgl: Fix dkl link training José Roberto de Souza
2019-09-24 15:58 ` Imre Deak [this message]
2019-09-24 23:59 ` Souza, Jose
2019-09-25 15:25 ` Imre Deak
2019-09-23 19:55 ` [PATCH v3 8/9] drm/i915/tgl: Return the mg/dkl pll as DDI clock for new TC ports José Roberto de Souza
2019-09-23 22:07 ` Lucas De Marchi
2019-09-23 19:55 ` [PATCH v3 9/9] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
2019-09-23 22:08 ` Lucas De Marchi
2019-09-23 21:20 ` ✓ Fi.CI.BAT: success for TGL TC enabling (rev3) Patchwork
2019-09-24 10:48 ` ✓ Fi.CI.IGT: " Patchwork
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