From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: James Ausmus <james.ausmus@intel.com>
Cc: "Ville Syrjälä" <ville.syrjala@intel.com>,
intel-gfx@lists.freedesktop.org,
"Lucas De Marchi" <lucas.demarchi@intel.com>
Subject: Re: [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE
Date: Fri, 27 Sep 2019 21:01:39 +0300 [thread overview]
Message-ID: <20190927180139.GX1208@intel.com> (raw)
In-Reply-To: <20190925203352.9827-3-james.ausmus@intel.com>
On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
>
> BSpec: 49326
>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++-----
> 2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e752de9470bd..84ae6553485b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8865,6 +8865,7 @@ enum {
> #define GEN9_SAGV_DISABLE 0x0
> #define GEN9_SAGV_IS_DISABLED 0x1
> #define GEN9_SAGV_ENABLE 0x3
> +#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> #define GEN6_PCODE_DATA _MMIO(0x138128)
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5ad72dcb0faa..ca2bec09edb5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3665,16 +3665,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> static int
> intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
> {
> - int sagv_block_time_us = 1000; /* Default to unusable block time */
> + uint val = 0;
uint?
> + int ret, sagv_block_time_us = 1000; /* Default to unusable block time */
val+ret could live in a tighter scope.
>
> - if (IS_GEN(dev_priv, 11))
> + if (INTEL_GEN(dev_priv) >= 12) {
> + ret = sandybridge_pcode_read(dev_priv,
> + GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> + &val, NULL);
We should probably stash this somewhere so we don't have to keep
asking pcode about it every single time.
Magic numbers look correct
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + if (!ret)
> + sagv_block_time_us = val;
> + else
> + DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> + } else if (IS_GEN(dev_priv, 11)) {
> sagv_block_time_us = 10;
> - else if (IS_GEN(dev_priv, 10))
> + } else if (IS_GEN(dev_priv, 10)) {
> sagv_block_time_us = 20;
> - else if (IS_GEN(dev_priv, 9))
> + } else if (IS_GEN(dev_priv, 9)) {
> sagv_block_time_us = 30;
> - else
> + } else {
> MISSING_CASE(INTEL_GEN(dev_priv));
> + }
>
> return sagv_block_time_us;
> }
> --
> 2.22.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2019-09-27 18:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-25 20:33 Add support for TGL in SAGV code paths James Ausmus
2019-09-25 20:33 ` [PATCH 1/3] drm/i915: Extract SAGV block time function James Ausmus
2019-09-27 17:51 ` Ville Syrjälä
2019-09-25 20:33 ` [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE James Ausmus
2019-09-27 18:01 ` Ville Syrjälä [this message]
2019-09-27 18:18 ` Ville Syrjälä
2019-09-25 20:33 ` [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV James Ausmus
2019-09-26 12:34 ` Ville Syrjälä
2019-09-27 17:16 ` James Ausmus
2019-09-25 21:02 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Extract SAGV block time function Patchwork
2019-09-25 21:25 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-26 16:23 ` ✓ Fi.CI.IGT: " Patchwork
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