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From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: nanley.g.chery@intel.com, dhinakaran.pandiyan@intel.com,
	ville.syrjala@intel.com
Subject: [PATCH v4 05/10] drm/i915: Extract framebufer CCS offset checks into a function
Date: Mon, 14 Oct 2019 17:05:28 -0700	[thread overview]
Message-ID: <20191015000533.11425-6-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20191015000533.11425-1-radhakrishna.sripada@intel.com>

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
 1 file changed, 40 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1dccca6a03d..be61dfdebb34 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2677,6 +2677,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	int hsub = fb->format->hsub;
+	int vsub = fb->format->vsub;
+	int tile_width, tile_height;
+	int ccs_x, ccs_y;
+	int main_x, main_y;
+
+	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+	tile_width *= hsub;
+	tile_height *= vsub;
+
+	ccs_x = (x * hsub) % tile_width;
+	ccs_y = (y * vsub) % tile_height;
+	main_x = intel_fb->normal[0].x % tile_width;
+	main_y = intel_fb->normal[0].y % tile_height;
+
+	/*
+	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
+	 * x/y offsets must match between CCS and the main surface.
+	 */
+	if (main_x != ccs_x || main_y != ccs_y) {
+		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+			      main_x, main_y,
+			      ccs_x, ccs_y,
+			      intel_fb->normal[0].x,
+			      intel_fb->normal[0].y,
+			      x, y);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int
 intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		   struct drm_framebuffer *fb)
@@ -2708,35 +2745,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		}
 
 		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			int hsub = fb->format->hsub;
-			int vsub = fb->format->vsub;
-			int tile_width, tile_height;
-			int main_x, main_y;
-			int ccs_x, ccs_y;
-
-			intel_tile_dims(fb, i, &tile_width, &tile_height);
-
-			tile_width *= hsub;
-			tile_height *= vsub;
-
-			ccs_x = (x * hsub) % tile_width;
-			ccs_y = (y * vsub) % tile_height;
-			main_x = intel_fb->normal[0].x % tile_width;
-			main_y = intel_fb->normal[0].y % tile_height;
-
-			/*
-			 * CCS doesn't have its own x/y offset register, so the intra CCS tile
-			 * x/y offsets must match between CCS and the main surface.
-			 */
-			if (main_x != ccs_x || main_y != ccs_y) {
-				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
-					      main_x, main_y,
-					      ccs_x, ccs_y,
-					      intel_fb->normal[0].x,
-					      intel_fb->normal[0].y,
-					      x, y);
-				return -EINVAL;
-			}
+			ret = intel_fb_check_ccs_xy(fb, x, y);
+			if (ret)
+				return ret;
 		}
 
 		/*
-- 
2.20.1

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  parent reply	other threads:[~2019-10-15  0:03 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-15  0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 02/10] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 04/10] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
2019-10-15  0:05 ` Radhakrishna Sripada [this message]
2019-10-15  0:05 ` [PATCH v4 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 07/10] drm/fb: Extend format_info member arrays to handle four planes Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 08/10] Gen-12 display can decompress surfaces compressed by the media engine Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
2019-10-15  0:47   ` Radhakrishna Sripada
2019-10-23  0:09     ` [PATCH v5 " Radhakrishna Sripada
2019-10-24  0:00       ` Chery, Nanley G
2019-10-24  0:00         ` [Intel-gfx] " Chery, Nanley G
2019-10-28 18:58       ` [PATCH v6 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression Radhakrishna Sripada
2019-10-28 18:58         ` [Intel-gfx] " Radhakrishna Sripada
2019-10-15  0:05 ` [PATCH v4 " Radhakrishna Sripada
2019-10-22 18:15   ` Matt Roper
2019-10-22 18:37     ` Sripada, Radhakrishna
2019-10-23  0:09   ` [PATCH v5 " Radhakrishna Sripada
2019-10-15  0:09 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev4) Patchwork
2019-10-15  0:34 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-15  1:08 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev5) Patchwork
2019-10-15  1:56 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-15 12:12 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-23  1:52 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev7) Patchwork
2019-10-23  2:35 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-23 17:20 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-23 17:20   ` [Intel-gfx] " Patchwork

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