From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Nanley G Chery <nanley.g.chery@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
dri-devel@lists.freedesktop.org,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [Intel-gfx] [PATCH 5/7] drm/framebuffer: Format modifier for Intel Gen-12 media compression
Date: Wed, 1 Jan 2020 01:37:54 +0200 [thread overview]
Message-ID: <20191231233756.18753-6-imre.deak@intel.com> (raw)
In-Reply-To: <20191231233756.18753-1-imre.deak@intel.com>
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
v2: Update code comment describing the color plane order for YUV
semiplanar formats.
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..8bc0b31597d8 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-12-31 23:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 1/7] drm/i915: Add support for non-power-of-2 FB plane alignment Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned Imre Deak
2020-01-02 14:12 ` Kahola, Mika
2019-12-31 23:37 ` [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error Imre Deak
2020-01-02 11:50 ` Kahola, Mika
2019-12-31 23:37 ` [Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes Imre Deak
2020-01-02 13:48 ` Kahola, Mika
2019-12-31 23:37 ` Imre Deak [this message]
2019-12-31 23:37 ` [Intel-gfx] [PATCH 6/7] drm/fb: Extend format_info member arrays to handle four planes Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 7/7] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine Imre Deak
2020-01-06 15:58 ` Radhakrishna Sripada
2020-01-01 0:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Media decompression support Patchwork
2020-01-01 0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-01 7:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-01-07 11:57 ` Imre Deak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191231233756.18753-6-imre.deak@intel.com \
--to=imre.deak@intel.com \
--cc=dhinakaran.pandiyan@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
--cc=nanley.g.chery@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox