From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Anshuamn Gupta <anshuman.gupta@intel.com>
Cc: intel-gfx@freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: add Wa_14010594013: icl,ehl
Date: Fri, 10 Jan 2020 10:54:09 -0800 [thread overview]
Message-ID: <20200110185409.GA3115813@intel.com> (raw)
In-Reply-To: <20200110090303.GA23528@intel.com>
On Fri, Jan 10, 2020 at 02:33:04PM +0530, Anshuamn Gupta wrote:
> On 2020-01-10 at 03:51:49 -0500, Matt Atwood wrote:
> > The bspec tells us we need to set this bit to avoid potential underruns.
> >
> > Bspec: 33450
> > Bspec: 33451
> > Bspec: 33452
> It would be nice to add index 7386 which is having the bit for PMRSP.
Indeed. In the end 7386 was the only one that I needed here.
(Besides the HSD article)
Probably even better to have only the 7386. But up to Matt.
> >
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index cf770793be54..b9dc5e2ea606 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7785,6 +7785,7 @@ enum {
> >
> > #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> > #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
> > +#define CNL_DELAY_PMRSP (1 << 22)
> > #define MASK_WAKEMEM (1 << 13)
> > #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 148ac455dfa7..10714d43e8a3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6610,6 +6610,10 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> > /* Wa_1407352427:icl,ehl */
> > intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
> > 0, PSDUNIT_CLKGATE_DIS);
> > +
> > + /*Wa_14010594013:icl, ehl */
> > + I915_WRITE(GEN8_CHICKEN_DCPR_1,
> > + I915_READ(GEN8_CHICKEN_DCPR_1) | CNL_DELAY_PMRSP);
> Is there any functional difference between Wa_14010594013 and above Wa_1407352427
I couldn't find any hsd article with this new number....
The one that Matt used seemed the correct one because it was the one
with all the info that I needed.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> using different family of writes, may be not related to this patch.
> Thanks,
> Anshuman Gupta.
> > }
> >
> > static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> > --
> > 2.21.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-01-10 18:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-10 8:51 [Intel-gfx] [PATCH] drm/i915: add Wa_14010594013: icl,ehl Matt Atwood
2020-01-10 1:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-01-10 9:03 ` [Intel-gfx] [PATCH] " Anshuamn Gupta
2020-01-10 18:54 ` Rodrigo Vivi [this message]
2020-01-13 11:51 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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