Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Jan 30, 2020 at 11:20:00AM -0800, Daniele Ceraolo Spurio wrote:
> 
> 
> On 1/30/20 6:08 AM, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2020-01-30 13:58:13)
> >> On Thu, Jan 30, 2020 at 01:37:49PM +0000, Chris Wilson wrote:
> >>> Quoting Patchwork (2020-01-30 06:49:28)
> >>>> #### Possible regressions ####
> >>>>
> >>>>    * igt@i915_selftest@live_active:
> >>>>      - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
> >>>>     [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_active.html
> >>>>     [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_active.html
> >>>
> >>> Well it works on Crestline. Broadwater snafu?
> >>
> >> Does the w/a thing actually work correctly for masked registers?
> >> It look to use rmw even for masked registers and IIRC some masked
> >> registers return 0xffff for the mask when read. I lost track of the
> >> values and masks being passed around before I got down that deep so
> >> can't immediatly see if the code is guaranteed to set only the
> >> expected mask bit(s) for the write.
> 
> But does it make any difference is the mask is returned or not with rmw? 
> if it is, we reprogram the lower 16 bits with the original value + our 
> diff, while if it isn't we just toggle in place the bit we're interested 
> in. The result should be the same in both cases.

Some bits can also have side effects (eg. sync flush trigger bits and
whatnot).

-- 
Ville Syrjälä
Intel
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