Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"De Marchi, Lucas" <lucas.demarchi@intel.com>,
	"Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/dgfx: Do not write in removed FBC fence registers
Date: Tue, 4 Feb 2020 15:47:41 +0200	[thread overview]
Message-ID: <20200204134741.GK13686@intel.com> (raw)
In-Reply-To: <3ab6b8071f4af31d0c6059748c6b5c54bfabd587.camel@intel.com>

On Tue, Feb 04, 2020 at 02:06:23AM +0000, Souza, Jose wrote:
> On Wed, 2020-01-29 at 13:42 +0200, Ville Syrjälä wrote:
> > On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza
> > wrote:
> > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > 
> > > dgfx platforms do not support CPU fence and FBC host tracking so
> > > lets avoid write to removed registers.
> > > 
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com
> > > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++-
> > >  1 file changed, 6 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index 1f0d24a1dec1..12900b8ce28e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct
> > > drm_i915_private *dev_priv)
> > >  		break;
> > >  	}
> > >  
> > > -	if (params->fence_id >= 0) {
> > > +	if (IS_DGFX(dev_priv)) {
> > > +		/*
> > > +		 * dGFX GPUs don't have apperture or fences and only
> > > rely on FBC
> > > +		 * render nuke to track frontbuffer modifications
> > > +		 */
> > > +	} else if (params->fence_id >= 0) {
> > >  		dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
> > >  		intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
> > >  			       SNB_CPU_FENCE_ENABLE | params-
> > > >fence_id);
> > 
> > if (fence) {
> > 	do stuff
> > } else if (num_fences) {
> > 	do other stuff
> > }
> 
> Did not get what you want here.

Don't add a silly looking empty if block.

And don't make the assumption that dgfx is the only thing that
has no fences, instead actually check if we have fences or not.

> It is covering all cases:
> - DGFX that don't have the registers
> - Setting the registers when fence_id >= 0
> - Clearing the register when fences_id == -1
> 
> > 
> > > -- 
> > > 2.25.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-02-04 13:47 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-28 23:52 [Intel-gfx] [PATCH 1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ José Roberto de Souza
2020-01-28 23:52 ` [Intel-gfx] [PATCH 2/2] drm/i915/dgfx: Do not write in removed FBC fence registers José Roberto de Souza
2020-01-29 11:42   ` Ville Syrjälä
2020-02-04  2:06     ` Souza, Jose
2020-02-04 13:47       ` Ville Syrjälä [this message]
2020-01-29  3:19 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ Patchwork
2020-01-29 11:44 ` [Intel-gfx] [PATCH 1/2] " Ville Syrjälä
2020-01-29 11:58   ` Ville Syrjälä
2020-02-04  1:42     ` Souza, Jose
2020-01-30  2:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ (rev2) Patchwork
2020-02-04 20:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ (rev3) Patchwork
2020-02-06 20:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200204134741.GK13686@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=dhinakaran.pandiyan@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jose.souza@intel.com \
    --cc=lucas.demarchi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox