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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when clearing DDI select
Date: Tue, 4 Feb 2020 20:19:10 +0200	[thread overview]
Message-ID: <20200204181910.GD13686@intel.com> (raw)
In-Reply-To: <0abaa6b7a8051e14e676f3c30343b14b3d315f65.camel@intel.com>

On Tue, Feb 04, 2020 at 05:48:24PM +0000, Souza, Jose wrote:
> On Tue, 2020-02-04 at 15:35 +0200, Ville Syrjälä wrote:
> > On Mon, Feb 03, 2020 at 02:55:49PM -0800, José Roberto de Souza
> > wrote:
> > > TGL is suffering of timeouts and fifo underruns when disabling
> > > transcoder in MST mode, this is fixed by set TRANS_DDI_MODE_SELECT
> > > to
> > > 0(HDMI mode) when clearing DDI select.
> > > 
> > > Although BSpec disable sequence don't require this step, it is a
> > > harmless change and it is also done by Windows driver.
> > > Anyhow HW team was notified about that but it can take some time to
> > > documentation to be updated.
> > > 
> > > A case that always lead to those issues is:
> > > - do a modeset enabling pipe A and pipe B in the same MST stream
> > > leaving A as master
> > > - disable pipe A, promote B as master doing a full modeset in A
> > > - enable pipe A, changing the master transcoder back to A(doing a
> > > full modeset in B)
> > > - Pow: underruns and timeouts
> > > 
> > > The transcoders involved will only work again when complete
> > > disabled
> > > and their power wells turned off causing a reset in their
> > > registers.
> > > 
> > > v2: Setting TRANS_DDI_MODE_SELECT to default when clearing DDI
> > > select
> > > not anymore when disabling TRANS_DDI, both work but this one looks
> > > more safe. (Ville comment)
> > 
> > I presume this still fixes the issue?
> 
> It does.
> 
> > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++--
> > >  1 file changed, 5 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index aa066fb9eb00..45082e71262c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1988,10 +1988,12 @@ void
> > > intel_ddi_disable_transcoder_func(const struct intel_crtc_state
> > > *crtc_state
> > >  	val &= ~TRANS_DDI_FUNC_ENABLE;
> > >  
> > >  	if (INTEL_GEN(dev_priv) >= 12) {
> > > -		if (!intel_dp_mst_is_master_trans(crtc_state))
> > > +		if (!intel_dp_mst_is_master_trans(crtc_state)) {
> > >  			val &= ~TGL_TRANS_DDI_PORT_MASK;
> > > +			val &= ~TRANS_DDI_MODE_SELECT_MASK;
> > 
> > Two separate statements.
> > 
> > > +		}
> > >  	} else {
> > > -		val &= ~TRANS_DDI_PORT_MASK;
> > > +		val &= ~(TRANS_DDI_PORT_MASK |
> > > TRANS_DDI_MODE_SELECT_MASK);
> > 
> > One statement.
> 
> Here was the only place that fitted in 80 cols.

'\n' is a thing.

val &= ~(A |
         B);

> 
> > 
> > >  	}
> > >  	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
> > > val);
> > >  
> > > @@ -3729,6 +3731,7 @@ static void intel_ddi_post_disable_dp(struct
> > > intel_encoder *encoder,
> > >  			val = intel_de_read(dev_priv,
> > >  					    TRANS_DDI_FUNC_CTL(cpu_tran
> > > scoder));
> > >  			val &= ~TGL_TRANS_DDI_PORT_MASK;
> > > +			val &= ~TRANS_DDI_MODE_SELECT_MASK;
> > 
> > Two again.
> > 
> > A bit inconsistent, otherwise lgtm.
> > 
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Thanks
> 
> > 
> > >  			intel_de_write(dev_priv,
> > >  				       TRANS_DDI_FUNC_CTL(cpu_transcode
> > > r),
> > >  				       val);
> > > -- 
> > > 2.25.0

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-02-04 18:19 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-03 22:55 [Intel-gfx] [PATCH v2] drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when clearing DDI select José Roberto de Souza
2020-02-04 13:35 ` Ville Syrjälä
2020-02-04 17:48   ` Souza, Jose
2020-02-04 18:19     ` Ville Syrjälä [this message]
2020-02-04 20:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-02-06 19:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-02-06 21:20   ` Souza, Jose

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