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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V14)
Date: Wed, 26 Feb 2020 16:30:21 +0200	[thread overview]
Message-ID: <20200226143021.GI13686@intel.com> (raw)
In-Reply-To: <20200219211551.20125-2-bob.j.paauwe@intel.com>

On Wed, Feb 19, 2020 at 01:15:51PM -0800, Bob Paauwe wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
> 
> v2: Edited commit message, removed redundant whitespaces.
> 
> v3: Fixed fallthrough logic for the format switch cases.
> 
> v4: Yet again fixed fallthrough logic, to reuse code from other case
>     labels.
> 
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> 
> v6: Removed unneeded initializer for new XYUV format.
> 
> v7: Added scaling support for DRM_FORMAT_XYUV
> 
> v8: Edited commit message to be more clear about skl+, renamed
>     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
>     doesn't support per-pixel alpha. Fixed minor code issues.
> 
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
> 
> v10: Added missing XYUV format to sprite planes for skl+.
> 
> v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
> 
> v12: Fixed rebase conflicts
> 
> V13: Rebased.
>      Added format to ICL format lists.
> 
> V14: Added format to TGL format lists.
>      Rebased.
> 
> v12:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
>  drivers/gpu/drm/i915/display/intel_sprite.c  | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  3 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 61ba1f2256a0..919270b7e240 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3331,6 +3331,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  		return DRM_FORMAT_RGB565;
>  	case PLANE_CTL_FORMAT_NV12:
>  		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_XYUV:
> +		return DRM_FORMAT_XYUV8888;
>  	case PLANE_CTL_FORMAT_P010:
>  		return DRM_FORMAT_P010;
>  	case PLANE_CTL_FORMAT_P012:
> @@ -4570,6 +4572,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
>  	case DRM_FORMAT_XRGB16161616F:
>  	case DRM_FORMAT_ARGB16161616F:
>  		return PLANE_CTL_FORMAT_XRGB_16161616F;
> +	case DRM_FORMAT_XYUV8888:
> +		return PLANE_CTL_FORMAT_XYUV;
>  	case DRM_FORMAT_YUYV:
>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>  	case DRM_FORMAT_YVYU:
> @@ -6186,6 +6190,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV8888:
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 7abeefe8dce5..8a95a1e7448a 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2483,6 +2483,7 @@ static const u32 skl_plane_formats[] = {
>  	DRM_FORMAT_YVYU,
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_XYUV8888,
>  };
>  
>  static const u32 skl_planar_formats[] = {
> @@ -2501,6 +2502,7 @@ static const u32 skl_planar_formats[] = {
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
>  	DRM_FORMAT_NV12,
> +	DRM_FORMAT_XYUV8888,
>  };
>  
>  static const u32 glk_planar_formats[] = {
> @@ -2572,6 +2574,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
>  	DRM_FORMAT_XVYU2101010,
>  	DRM_FORMAT_XVYU12_16161616,
>  	DRM_FORMAT_XVYU16161616,
> +	DRM_FORMAT_XYUV8888,

Would be more consistent if this was placed just before
DRM_FORMAT_XVYU2101010 in all cases.

Also we seem to be missing glk_planar_formats[] and
icl_sdr_y_plane_formats[] entirely.

>  };
>  
>  static const u32 icl_hdr_plane_formats[] = {
> @@ -2603,6 +2606,7 @@ static const u32 icl_hdr_plane_formats[] = {
>  	DRM_FORMAT_XVYU2101010,
>  	DRM_FORMAT_XVYU12_16161616,
>  	DRM_FORMAT_XVYU16161616,
> +	DRM_FORMAT_XYUV8888,
>  };
>  
>  static const u64 skl_plane_format_modifiers_noccs[] = {
> @@ -2770,6 +2774,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV8888:
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> @@ -2834,6 +2839,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV8888:
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b09c1d6dc0aa..17e6453d31d7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6768,7 +6768,7 @@ enum {
>  #define   PLANE_CTL_FORMAT_P012			(5 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
>  #define   PLANE_CTL_FORMAT_P016			(7 << 24)
> -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
> +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
>  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
>  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-02-26 14:30 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-19 21:15 [Intel-gfx] [PATCH 0/1] Adding YUV444 packed format support for skl+ Bob Paauwe
2020-02-19 21:15 ` [Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V14) Bob Paauwe
2020-02-26 14:30   ` Ville Syrjälä [this message]
2020-02-27 19:15   ` [Intel-gfx] [PATCH 0/1] Adding YUV444 packed format support for skl+ Bob Paauwe
2020-02-27 19:15     ` [Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V15) Bob Paauwe
2020-02-19 21:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Adding YUV444 packed format support for skl+ (rev3) Patchwork
2020-02-19 21:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-21 18:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-02-24  9:20   ` Shankar, Uma
2020-02-24  9:44     ` Peres, Martin
2020-02-24 17:56       ` Vudum, Lakshminarayana
2020-02-24 16:25 ` Patchwork
2020-02-24 16:50 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-02-26 10:51   ` Shankar, Uma
2020-02-28  0:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Adding YUV444 packed format support for skl+ (rev4) Patchwork
2020-02-28  1:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-29  9:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-05 18:00   ` Bob Paauwe
2020-03-11 14:23     ` Shankar, Uma

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